Computing in the dark silicon era: Current trends and research challenges
M Shafique, S Garg - IEEE Design & Test, 2016 - ieeexplore.ieee.org
Computing in the Dark Silicon Era: Current Trends and Research Challenges Page 1 2168-2356
(c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE …
(c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE …
A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology
Ultra-low power operation and extreme energy efficiency are strong requirements for a
number of high-growth application areas, such as E-health, Internet of Things, and wearable …
number of high-growth application areas, such as E-health, Internet of Things, and wearable …
[图书][B] Power Management Techniques for Integrated Circuit Design
KH Chen - 2016 - books.google.com
This book begins with the premise that energy demands are directing scientists towards ever-
greener methods of power management, so highly integrated power control ICs (integrated …
greener methods of power management, so highly integrated power control ICs (integrated …
193 MOPS/mW@ 162 MOPS, 0.32 V to 1.15 V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
Low power (mW) and high performance (GOPS) are strong requirements for compute-
intensive signal processing in E-health, Internet-of-Things, and wearable applications. This …
intensive signal processing in E-health, Internet-of-Things, and wearable applications. This …
Near threshold voltage (NTV) computing: Computing in the dark silicon era
Near-threshold computing has emerged as an attractive paradigm for energy efficiency. This
article discusses challenges and opportunities for designing complex system on chips that …
article discusses challenges and opportunities for designing complex system on chips that …
Ultra low voltage synthesizable memories: A trade-off discussion in 65 nm CMOS
O Andersson, B Mohammadi… - … on Circuits and …, 2016 - ieeexplore.ieee.org
In this study, design considerations for ultra low voltage (ULV) standard-cell based
memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and …
memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and …
Challenges and designs of tfet for digital applications
This chapter reviews the challenges and designs of digital TFET circuits. Several
fundamental features of TFET such as unidirectional conduction, delayed saturation, and …
fundamental features of TFET such as unidirectional conduction, delayed saturation, and …
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment
This paper presents DynOR, a 32-bit 6-stage Open-RISC microprocessor with dynamic clock
adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the …
adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the …
ScalCore: Designing a core for voltage scalability
B Gopireddy, C Song, J Torrellas… - … Symposium on High …, 2016 - ieeexplore.ieee.org
Upcoming multicores need to provide increasingly stringent energy-efficient execution
modes. Currently, energy efficiency is attained by lowering the voltage (V dd) through DVFS …
modes. Currently, energy efficiency is attained by lowering the voltage (V dd) through DVFS …
Subthreshold operation of CAAC-IGZO FPGA by overdriving of programmable routing switch and programmable power switch
M Kozuma, Y Okamoto, T Nakagawa… - … Transactions on Very …, 2016 - ieeexplore.ieee.org
A field-programmable gate array (FPGA) using a crystalline oxide semiconductor of c-axis-
aligned crystal indium-gallium-zinc oxide (CAAC-IGZO) has been developed, which is …
aligned crystal indium-gallium-zinc oxide (CAAC-IGZO) has been developed, which is …