Low-cost inter-linked subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
This paper introduces a new DRAM design that enables fast and energy-efficient bulk data
movement across subarrays in a DRAM chip. While bulk data movement is a key operation …
movement across subarrays in a DRAM chip. While bulk data movement is a key operation …
Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …
latency is defined by three fundamental operations that take place within the DRAM cell …
PARBOR: An efficient system-level technique to detect data-dependent failures in DRAM
System-level detection and mitigation of DRAM failures offer a variety of system
enhancements, such as better reliability, scalability, energy, and performance. Unfortunately …
enhancements, such as better reliability, scalability, energy, and performance. Unfortunately …
Counter-based tree structure for row hammering mitigation in DRAM
SM Seyedzadeh, AK Jones… - IEEE Computer …, 2016 - ieeexplore.ieee.org
Scaling down DRAM technology degrades cell reliability due to increased coupling between
adjacent DRAM cells, commonly referred to as crosstalk. Moreover, high access frequency …
adjacent DRAM cells, commonly referred to as crosstalk. Moreover, high access frequency …
Buddy-RAM: Improving the performance and efficiency of bulk bitwise operations using DRAM
Bitwise operations are an important component of modern day programming. Many widely-
used data structures (eg, bitmap indices in databases) rely on fast bitwise operations on …
used data structures (eg, bitmap indices in databases) rely on fast bitwise operations on …
A case for memory content-based detection and mitigation of data-dependent failures in DRAM
DRAM cells in close proximity can fail depending on the data content in neighboring cells.
These failures are called data-dependent failures. Detecting and mitigating these failures …
These failures are called data-dependent failures. Detecting and mitigating these failures …
A case for toggle-aware compression for GPU systems
Data compression can be an effective method to achieve higher system performance and
energy efficiency in modern data-intensive applications by exploiting redundancy and data …
energy efficiency in modern data-intensive applications by exploiting redundancy and data …
Reducing DRAM latency at low cost by exploiting heterogeneity
D Lee - arXiv preprint arXiv:1604.08041, 2016 - arxiv.org
In modern systems, DRAM-based main memory is significantly slower than the processor.
Consequently, processors spend a long time waiting to access data from main memory …
Consequently, processors spend a long time waiting to access data from main memory …
The processing using memory paradigm: In-DRAM bulk copy, initialization, bitwise AND and OR
V Seshadri, O Mutlu - arXiv preprint arXiv:1610.09603, 2016 - arxiv.org
In existing systems, the off-chip memory interface allows the memory controller to perform
only read or write operations. Therefore, to perform any operation, the processor must first …
only read or write operations. Therefore, to perform any operation, the processor must first …
Simple dram and virtual memory abstractions to enable highly efficient memory systems
V Seshadri - arXiv preprint arXiv:1605.06483, 2016 - arxiv.org
In most modern systems, the memory subsystem is managed and accessed at multiple
different granularities at various resources. We observe that such multi-granularity …
different granularities at various resources. We observe that such multi-granularity …