Fault-tolerant dynamic task mapping and scheduling for network-on-chip-based multicore platform

N Chatterjee, S Paul, S Chattopadhyay - ACM Transactions on …, 2017 - dl.acm.org
In Network-on-Chip (NoC)-based multicore systems, task allocation and scheduling are
known to be important problems, as they affect the performance of applications in terms of …

Self-healing router architecture for reliable network-on-chips

K Khalil, O Eldash, M Bayoumi - 2017 24th IEEE International …, 2017 - ieeexplore.ieee.org
NoCs are a well established research topic and several Implementations have been
proposed for Self-healing. Self-healing refers to the ability of a system to detect faults or …

Review of network on chip architectures

M Athar Javed Sethi, F Azmadi Hussin… - Recent Advances in …, 2017 - ingentaconnect.com
Background: Network on Chip (NoC) is a communication mechanism to provide scalable,
modular, robust and high-performance communication for the on-chip network. Switching …

Handling scheduling uncertainties through traffic shaping in time-triggered train networks

Q Yu, X Zhao, H Wan, Y Gao, C Lu… - 2017 IEEE/ACM 25th …, 2017 - ieeexplore.ieee.org
While trains traditionally relied on field bus to support real-time control applications, next-
generation trains are moving toward Ethernet as an integrated, high-bandwidth …

Mechanisms to provide fault tolerance to a network-on-chip

TF Pereira, DR de Melo, EA Bezerra… - IEEE Latin America …, 2017 - ieeexplore.ieee.org
The constant reduction in the components size of integrated circuits, as well as higher
operating frequencies, increases the vulnerability to internal and external noise sources …

Bio-inspired fault tolerant network on chip

MAJ Sethi, FA Hussin, NH Hamid - Integration, 2017 - Elsevier
The integration of heterogeneous processing elements (PEs) or nodes in the System on
Chip (SoC) has made the communication structure very complex. The bus based system …

A local reconfiguration based scalable fault tolerant many-processor array

S Banerjee, W Rao - 2017 22nd Asia and South Pacific Design …, 2017 - ieeexplore.ieee.org
This paper presents a reconfigurable Many-processor Array utilizing a layer of Routers with
localized interconnects to provide fault tolerance for Processing Elements (PEs). In such a …

Fault tolerance design for NoCs: Partial virtual-channel sharing

S Abed, M AlShayeji, Z Abdullah… - Proceedings of the 6th …, 2017 - dl.acm.org
As the industry of Network of Chips (NoCs) evolves, the reliability and performance of these
systems are becoming more critical requirement. The fault tolerance issue is an essential …

[PDF][PDF] Structural redundancy and design space exploration method for the hardware components with fault mitigation design

V Rozanov, E Suvorova - FRUCT 20, 2017 - fruct.org
Fault mitigation for modern embedded systems is a necessary feature due to accelerating
aging and manufacturing defects, which diagnosis during the chip testing at fabric is …

Latency reduction of fault-tolerant NoCs by employing multiple paths

RTP Milfont, RG Mota, JM Ferreira, PC Cortez… - Proceedings of the 30th …, 2017 - dl.acm.org
Digital circuit technologies at nanoscale levels increase the likelihood of permanent,
transient and intermittent faults. As a result, the demand for fault tolerance strategies is the …