Quantum engineering entails atom-by-atom design and fabrication of electronic devices.
This innovative technology that unifies materials science and device engineering has been …

A 23.6-Mb/mm 2 and a 20.4-Mb/mm 2 SRAM arrays are manufactured in a 10-nm FinFET
CMOS technology, utilizing high-density 0.0312 μm 2 and low-voltage 0.0367 μm 2 6T …

Carbon nanotube FETs (CNFETs) promise significant energy efficiency benefits versus
silicon for digital systems. While these projected benefits are for CNFETs with similar …

In this paper, we propose a trench MOS architecture for the upcoming 5 nm node and
beyond logic transistor. The intended device has a gate formed vertically downward, with …

We present a hierarchical methodology using a combination of ab-initio phonon scattering,
electron transmission, and multi-scale finite element simulations to accurately model …

Researchers lacking access to suitable commercial SPICE models have widely used
predictive technology models (PTMs) for simulation experiments in advanced technologies …

This article presents an atomic force microscopy (AFM) technique for true three‐dimensional
(3D) characterization. The cantilever probe with flared tip was used in a home‐made 3D …

As transistor size continues to shrink, SiO2/polysilicon gate stack has been replaced by high-
k/metal gate to enable further scaling. Two different integration approaches have been …

Continuous CMOS scaling is being driven by innovation of novel device architectures to
improve device performances at lower power consumption 1. However, middle-of-the-line …

III-V devices have been actively explored for high performance and low power logic
applications to replace silicon in the past decade, mainly owing to their higher intrinsic …