A novel ultra low power accuracy configurable adder at transistor level
AM Hassani, M Rezaalipour… - 2018 8th International …, 2018 - ieeexplore.ieee.org
Low power consumption, nowadays, has emerged to be an indispensable factor as there is
a growing demand for designing efficient computation-intensive systems and integrating …
a growing demand for designing efficient computation-intensive systems and integrating …
Low Power Adder Circuit Based on Coupling Technique
A Roy, A Sharma, A Mehra, SK Rajput - Intelligent Communication, Control …, 2018 - Springer
Today's technology is continuously scaling itself, thereby resulting in increasing density of
the transistors leading to high power dissipation on the chip. Therefore, we need to reduce …
the transistors leading to high power dissipation on the chip. Therefore, we need to reduce …
A FPGA Implementation of Hard Systematic Error Correcting codes based Matching of Data Encoded Architecture with Low-Complexity, Low-Latency
SB Shirol, S Ramakrishnan… - 2018 Second …, 2018 - ieeexplore.ieee.org
Nowadays to get error free data is toughest task. To verify whether the data is error free or
not and decrease overall area and latency the new architecture has been designed which …
not and decrease overall area and latency the new architecture has been designed which …
[引用][C] Layout designing of full adder with minimum number of transistors using 32nm CMOS technology
R Rani