GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies

JS Kim, D Senol Cali, H Xin, D Lee, S Ghose, M Alser… - BMC genomics, 2018 - Springer
Background Seed location filtering is critical in DNA read mapping, a process where billions
of DNA fragments (reads) sampled from a donor are mapped onto a reference genome to …

The DRAM latency PUF: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity DRAM devices

JS Kim, M Patel, H Hassan… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
Physically Unclonable Functions (PUFs) are commonly used in cryptography to identify
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …

What your DRAM power models are not telling you: Lessons from a detailed experimental study

S Ghose, AG Yaglikçi, R Gupta, D Lee… - Proceedings of the …, 2018 - dl.acm.org
Main memory (DRAM) consumes as much as half of the total system power in a computer
today, due to the increasing demand for memory capacity and bandwidth. There is a …

Solar-DRAM: Reducing DRAM access latency by exploiting the variation in local bitlines

J Kim, M Patel, H Hassan… - 2018 IEEE 36th …, 2018 - ieeexplore.ieee.org
DRAM latency is a major bottleneck for many applications in modern computing systems. In
this work, we rigorously characterize the effects of reducing DRAM access latency on 282 …

Enabling the adoption of processing-in-memory: Challenges, mechanisms, future research directions

S Ghose, K Hsieh, A Boroumand… - arXiv preprint arXiv …, 2018 - arxiv.org
Poor DRAM technology scaling over the course of many years has caused DRAM-based
main memory to increasingly become a larger system bottleneck. A major reason for the …

Reducing DRAM latency via charge-level-aware look-ahead partial restoration

Y Wang, A Tavakkol, L Orosa, S Ghose… - 2018 51st Annual …, 2018 - ieeexplore.ieee.org
Long DRAM access latency is a major bottleneck for system performance. In order to access
data in DRAM, a memory controller (1) activates (ie, opens) a row of DRAM cells in a cell …

[PDF][PDF] VRL-DRAM: improving DRAM performance via variable refresh latency.

A Das, H Hassan, O Mutlu - DAC, 2018 - people.inf.ethz.ch
ABSTRACT A DRAM chip requires periodic refresh operations to prevent data loss due to
charge leakage in DRAM cells. Refresh operations incur significant performance overhead …

Reliability issues in flash-memory-based solid-state drives: Experimental analysis, mitigation, recovery

Y Cai, S Ghose, EF Haratsch, Y Luo, O Mutlu - Inside Solid State Drives …, 2018 - Springer
NAND flash memory is ubiquitous in everyday life today because its capacity has
continuously increased and cost has continuously decreased over decades. This positive …

Minimizing retention induced refresh through exploiting process variation of flash memory

Y Di, L Shi, C Gao, Q Li, CJ Xue… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Refresh schemes have been the default approach in NAND flash memory to avoid data
losses. The critical issue of the refresh schemes is that they introduce additional costs on …

Farewell my shared llc! a case for private die-stacked dram caches for servers

A Shahab, M Zhu, A Margaritov… - 2018 51st Annual IEEE …, 2018 - ieeexplore.ieee.org
The slowdown in technology scaling mandates rethinking of conventional CPU architectures
in a quest for higher performance and new capabilities. This work takes a step in this …