Multipatterning technology used in 7-nm technology and beyond imposes more and more
complex design rules on the layout of cells. The often nonlocal nature of these new design …

Chemical composition of interfaces between physical-vapor-deposited TiN and SiO2 as
affected by introduction of a thin (0.5–3 nm) alumina interlayer was studied using …

First microprocessor released to the market in 1971 was consisting of 2300 transistors.
Following Moore's law less than five decades later consumer electronic chips consist of …

We report a novel nanocrystal-embedded-insulator (NEI) ferroelectric field-effect transistor
(FeFET) with very thin unified-ferroelectric/dielectric (FE/DE) insulating layer, which is …

This work presents a novel statistical-based general compact model for 7nm technology
node devices like FinFETs. Unlike conventional compact model based on less accurate …

In this paper, ideal Technology Computer Aided Design (TCAD) simulation is carried out for
small size FinFET transistors. The definition of device critical dimensions is close to the 4th …

The downscaling CMOS technology is down to and less than the 22-nm gate length regimes
unveiled the limitations of the planar bulk MOSFET. The 3-dimensional FinFET has then …

The MOL PC-CA TDDB reliability is systematically evaluated for the 1.98 V IO devices with
Self-Aligned Contact (SAC) and top off oxide process. Compared to the thin oxide devices …

Multi patterning technology used in 7nm technology and beyond imposes more and more
complex design rules on the layout of cells. The often non local nature of these new design …

Black phosphorus (BP), a layered 2D semiconductor that can be isolated to one monolayer
thicknesses re-emerged in 2014 because of its promise for use in applications such as high …