1.4 5G wireless communication: An inflection point

V Ilderem - 2019 IEEE international solid-state circuits …, 2019 - ieeexplore.ieee.org
The 5G era is upon us, ushering in new opportunities for technology innovation across the
computing and connectivity landscape. The advent of the Internet of Things has resulted in …

A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications

V Sharma, M Gopal, P Singh, SK Vishvakarma… - … Integrated Circuits and …, 2019 - Springer
With the increased requirement of on-chip data computations in internet of things based
applications, the embedded on-chip SRAM memory has been under its renovation stage to …

Designing vertical processors in monolithic 3D

B Gopireddy, J Torrellas - … of the 46th International Symposium on …, 2019 - dl.acm.org
A processor laid out vertically in stacked layers can benefit from reduced wire delays, low
energy consumption, and a small footprint. Such a design can be enabled by Monolithic 3D …

Predictable GPUs frequency scaling for energy and performance

K Fan, B Cosenza, B Juurlink - … of the 48th International Conference on …, 2019 - dl.acm.org
Dynamic voltage and frequency scaling (DVFS) is an important solution to balance
performance and energy consumption, and hardware vendors provide management …

Integrated power management for battery-indifferent systems with ultra-wide adaptation down to nW

L Lin, S Jain, M Alioto - IEEE Journal of Solid-State Circuits, 2019 - ieeexplore.ieee.org
This article presents a power management unit (PMU) enabling ultra-wide power-
performance tradeoff well beyond voltage scaling, and adaptation to the sensed …

A 290-mV, 7-nm ultra-Low-voltage one-port SRAM compiler design using a 12T write contention and read upset free bit-cell

ME Sinangil, YT Lin, HJ Liao… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
In this paper, we present an ultra-low voltage oneport static random access memory (SRAM)
compiler targeting small to medium array sizes to provide a smaller area solution compared …

Modeling and circuit design of associative memories with spin–orbit torque fets

O Afuye, X Li, F Guo, D Jena, DC Ralph… - IEEE Journal on …, 2019 - ieeexplore.ieee.org
This article introduces a circuits model for a proposed spin-based device called a spin–orbit
torque field-effect transistor (SOTFET) that can operate as a nonvolatile memory and logic …

[图书][B] Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors

H Reyserhove, W Dehaene - 2019 - books.google.com
This book enables readers to achieve ultra-low energy digital system performance. The
author's main focus is the energy consumption of microcontroller architectures in digital …

Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing

J Shiomi, T Ishihara, H Onodera - Integration, 2019 - Elsevier
This paper proposes a standard-cell based memory (SCM) as an alternative to a traditional
on-chip SRAM for near-threshold voltage computing. It focuses on area-and energy …

Adaptive energy optimal computing

S Solki - US Patent 10,416,746, 2019 - Google Patents
Methods, devices and systems are described that relate to an energy optimal computing
control system, where clock rates and supply voltage are control knobs to adjust the total …