The history of integrated circuit (IC) development is another record of human challenges
involving space. Efforts have been made to protect ICs from sudden malfunctions due to …

This article presents a comprehensive assessment on the 6T static random access memory
(SRAM) cell with 7-nm FinFET technology by implementing quantum physics-based device …

In this study, the negative DIBL (N-DIBL), negative differential resistance (NDR), and Miller
effect of a negative capacitance nanowire filed-effect-transistor (negative capacitance (NC) …

Due to the increasing importance and complexity of source/drain parasitic resistance (Rsd)
in nanoscale CMOS technology and circuit design, a predictive 3-D structure-aware Rsd …

Low‐dielectric constant (low‐k) material is critical for advanced FinFET technology parasitic
capacitance reduction to enable low‐power and high‐performance applications. Silicon …

This work presents a novel general compact model for 7-nm technology node devices like
FinFETs as an extension of previous conventional compact model that based on some less …

FinFET devices with and without LDD implantation has been studied for dimensions
compatible with leading 14nm technology node. Devices without LDD have better …

The total ionizing dose (TID) impacts are studied in charge-trapping (CT) type 3D NAND
flash memories with a MONOS (metal-oxide-nitride-oxide-silicon) cell structure and …

Speed or clock rate of the first microprocessor released to the market in 1971 was 740 kHz.
This microprocessor was intended for calculator application. Continuing increase of …

This article presents a device-circuit co-optimization on Negative Capacitance FinFETs (NC-
FinFETs). A physics-based SPICE model that combines industry-standard BSIM-CMG model …