After a plethora of high-profile RowHammer attacks, CPU and DRAM vendors scrambled to
deliver what was meant to be the definitive hardware solution against the RowHammer …

RowHammer is a circuit-level DRAM vulnerability, first rigorously analyzed and introduced in
2014, where repeatedly accessing data in a DRAM row can cause bit flips in nearby rows …

Main memory, composed of DRAM, is a performance bottleneck for many applications, due
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …

Cloud providers are concerned that Rowhammer poses a potentially critical threat to their
servers, yet today they lack a systematic way to test whether the DRAM used in their servers …

Recently proposed DRAM based memory-centric architectures have demonstrated their
great potentials in addressing the memory wall challenge of modern computing systems …

Increasing single-cell DRAM error rates have pushed DRAM manufacturers to adopt on-die
error-correction coding (ECC), which operates entirely within a DRAM chip to improve …

DRAM is the prevalent main memory technology, but its long access latency can limit the
performance of many workloads. Although prior works provide DRAM designs that reduce …

There are three domains in a modern thermally-constrained mobile system-on-chip (SoC):
compute, IO, and memory. We observe that a modern SoC typically allocates a fixed power …

In-situ approaches process data very close to the memory cells, in the row buffer of each
subarray. This minimizes data movement costs and affords parallelism across subarrays …

Computers continue to diversify with respect to system designs, emerging memory
technologies, and application memory demands. Unfortunately, continually adapting the …