Multi-core devices for safety-critical systems: A survey
Multi-core devices are envisioned to support the development of next-generation safety-
critical systems, enabling the on-chip integration of functions of different criticality. This …
critical systems, enabling the on-chip integration of functions of different criticality. This …
{PANIC}: A {High-Performance} programmable {NIC} for multi-tenant networks
Programmable NICs have diverse uses, and there is need for a NIC platform that can offload
computation from multiple co-resident applications to many different types of substrates …
computation from multiple co-resident applications to many different types of substrates …
Think fast: A tensor streaming processor (TSP) for accelerating deep learning workloads
D Abts, J Ross, J Sparling… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
In this paper, we introduce the Tensor Streaming Processor (TSP) architecture, a functionally-
sliced microarchitecture with memory units interleaved with vector and matrix deep learning …
sliced microarchitecture with memory units interleaved with vector and matrix deep learning …
Livia: Data-centric computing throughout the memory hierarchy
E Lockerman, A Feldmann, M Bakhshalipour… - Proceedings of the …, 2020 - dl.acm.org
In order to scale, future systems will need to dramatically reduce data movement. Data
movement is expensive in current designs because (i) traditional memory hierarchies force …
movement is expensive in current designs because (i) traditional memory hierarchies force …
T4: Compiling sequential code for effective speculative parallelization in hardware
Multicores are now ubiquitous, but programmers still write sequential code. Speculative
parallelization is an enticing approach to parallelize code while retaining the ease of …
parallelization is an enticing approach to parallelize code while retaining the ease of …
System-on-chip interface architecture
GHK Bilski, JJN Serra, D Clarke, T Tuan… - US Patent …, 2020 - Google Patents
A device may include a plurality of data processing engines, a subsystem, and an SoC
interface block coupled to the plurality of data processing engines and the subsystem. The …
interface block coupled to the plurality of data processing engines and the subsystem. The …
Engineer the channel and adapt to it: Enabling wireless intra-chip communication
Ubiquitous multicore processors nowadays rely on an integrated packet-switched network
for cores to exchange and share data. The performance of these intra-chip networks is a key …
for cores to exchange and share data. The performance of these intra-chip networks is a key …
Ironhide: A secure multicore that efficiently mitigates microarchitecture state attacks for interactive applications
Microprocessors enable aggressive hardware virtualization by means of which multiple
processes temporally execute on the system. These security-critical and ordinary processes …
processes temporally execute on the system. These security-critical and ordinary processes …
Reconfigurable network-on-chip security architecture
Growth of the Internet-of-things has led to complex system-on-chips (SoCs) being used in
the edge devices in IoT applications. The increased complexity is demanding designers to …
the edge devices in IoT applications. The increased complexity is demanding designers to …
Remote control: A simple deadlock avoidance scheme for modular systems-on-chip
Ever increasing performance demand and shrinking in the transistor size together result in
complex and dense packing in large chips. That motivates designers to opt for many small …
complex and dense packing in large chips. That motivates designers to opt for many small …