Sub-10 nm fabrication: methods and applications
Reliable fabrication of micro/nanostructures with sub-10 nm features is of great significance
for advancing nanoscience and nanotechnology. While the capability of current …
for advancing nanoscience and nanotechnology. While the capability of current …
Can ultra-thin Si FinFETs work well in the sub-10 nm gate-length region?
Fin field-effect transistors (FinFETs) dominate the present Si FETs. However, when the gate
length is scaled down to the sub-10 nm region, the experimental Si FinFETs suffer from poor …
length is scaled down to the sub-10 nm region, the experimental Si FinFETs suffer from poor …
An efficient ultra-low-power and superior performance design of ternary half adder using CNFET and gate-overlap TFET devices
S Vidhyadharan, SS Dan - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This paper presents a novel ultra-low power yet high-performance device and circuit design
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …
Toward monolithically integrated hybrid CMOS-NEM circuits
U Sikder, K Horace-Herron, TT Yen… - … on Electron Devices, 2021 - ieeexplore.ieee.org
Nanoelectromechanical (NEM) switches offer the advantages of zero OFF-state leakage
current, abrupt switching characteristics, nonvolatile (NV) operation, and relatively low ON …
current, abrupt switching characteristics, nonvolatile (NV) operation, and relatively low ON …
Ternary logic circuit based on negative capacitance field-effect transistors and its variation immunity
W Huang, H Zhu, Y Zhang, Z Wu, Q Huo… - … on Electron Devices, 2021 - ieeexplore.ieee.org
A multivalued logic (MVL) device can achieve greater data density with a smaller footprint
than a traditional binary logic device. In this study, a ternary logic inverter based on negative …
than a traditional binary logic device. In this study, a ternary logic inverter based on negative …
Investigation of negative DIBL effect for ferroelectric-based FETs to improve MOSFETs and CMOS circuits
W Huang, H Zhu, Y Zhang, Z Wu, K Jia, X Yin, Y Li… - Microelectronics …, 2021 - Elsevier
In this study, negative DIBL (NDIBL) due to negative capacitance is used to improve
MOSFETs and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) circuits by …
MOSFETs and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) circuits by …
Investigation on negative capacitance FinEFT beyond 7 nm node from device to circuit
J Huo, W Huang, F Zhang, S Zhang, W Gan… - Microelectronics …, 2021 - Elsevier
In this study, a SPICE model for Negative Capacitance FinFET (NC-FinFET) based on the
BSIM-CMG model and Landau-Khalatnikov (LK) equation is developed. The areas of the …
BSIM-CMG model and Landau-Khalatnikov (LK) equation is developed. The areas of the …
Mobility enhancement techniques for Ge and GeSn MOSFETs
The performance enhancement of conventional Si MOSFETs through device scaling is
becoming increasingly difficult. The application of high mobility channel materials is one of …
becoming increasingly difficult. The application of high mobility channel materials is one of …
Theoretical study of negative capacitance finfet with quasi-antiferroelectric material
F Zhang, Y Peng, X Deng, J Huo, Y Liu… - … on Electron Devices, 2021 - ieeexplore.ieee.org
In this work, a quasi-antiferroelectric (QAFE) model to precisely evaluate the electrical
characteristics of negative capacitance Fin field-effect transistor (NC-FinFET) integrated with …
characteristics of negative capacitance Fin field-effect transistor (NC-FinFET) integrated with …
An accurate process-induced variability-aware compact model-based circuit performance estimation for design-technology co-optimization
In sub-10-nm fin field-effect transistors (FinFETs), line-edge roughness (LER) and metal-
gate granularity (MGG) are the two most dominant sources of variability and are mostly …
gate granularity (MGG) are the two most dominant sources of variability and are mostly …