Comparison between conventional fast multipliers and improved fast multipliers using PTL Logic
M Bansal, V Bharti, V Chander - IOP Conference Series …, 2021 - iopscience.iop.org
Multiplier circuit is an important element in majority of the arithmetic operations. In the
domain of VLSI industry, obtaining low power consumption by the components and high …
domain of VLSI industry, obtaining low power consumption by the components and high …
High-speed hybrid tree multiplier hardware using modified Wallace and Dadda method
In this paper, we proposed an 8x8 Hybrid multiplier design using Dadda and Modified
Wallace methods. To achieve high-speed multiplication, two different algorithms are used …
Wallace methods. To achieve high-speed multiplication, two different algorithms are used …
Low Power, High Speed MUX Based Area Efficient Dadda Multiplier
K Da, P Nb, S Gb, P Db - Smart Intelligent Computing and …, 2021 - books.google.com
The multiplier is a fundamental building block in most digital ICs' arithmetic units. The
multiplier architecture in modern VLSI circuits must meet the main parameters of low power …
multiplier architecture in modern VLSI circuits must meet the main parameters of low power …