MeshUp: Stateless cache side-channel attack on CPU mesh
Cache side-channel attacks lead to severe security threats to the settings where a CPU is
shared across users, eg, in the cloud. The majority of attacks rely on sensing the micro …
shared across users, eg, in the cloud. The majority of attacks rely on sensing the micro …
Metasurface‐programmable wireless network‐on‐Chip
This paper introduces the concept of smart radio environments, currently intensely studied
for wireless communication in metasurface‐programmable meter‐scaled environments (eg …
for wireless communication in metasurface‐programmable meter‐scaled environments (eg …
A scalable architecture for reprioritizing ordered parallelism
Many algorithms schedule their work, or tasks, according to a priority order for correctness or
faster convergence. While priority schedulers commonly implement task enqueue and …
faster convergence. While priority schedulers commonly implement task enqueue and …
A survey on trusted distributed artificial intelligence
MA Ağca, S Faye, D Khadraoui - IEEE Access, 2022 - ieeexplore.ieee.org
Emerging Artificial Intelligence (AI) systems are revolutionizing computing and data
processing approaches with their strong impact on society. Data is processed with …
processing approaches with their strong impact on society. Data is processed with …
Agiler: An adaptive heterogeneous tile-based many-core architecture for risc-v processors
A Kamaleldin, D Göhringer - IEEE Access, 2022 - ieeexplore.ieee.org
Tile-based many-core architectures are extensively used in modern system-on-chip designs
to achieve scalable computing performance with adequate energy efficiency. Heterogeneity …
to achieve scalable computing performance with adequate energy efficiency. Heterogeneity …
SeVNoC: Security validation of system-on-chip designs with NoC fabrics
Modern System-on-Chip (SoC) designs include a variety of Network-on-Chip (NoC) fabrics
to implement coordination and communication of integrated hardware intellectual property …
to implement coordination and communication of integrated hardware intellectual property …
Efficient and scalable core multiplexing with M³v
N Asmussen, S Haas, C Weinhold, T Miemietz… - Proceedings of the 27th …, 2022 - dl.acm.org
The M³ system (ASPLOS'16) proposed a hardware/software co-design that simplifies
integration between general-purpose cores and special-purpose accelerators, allowing …
integration between general-purpose cores and special-purpose accelerators, allowing …
Power efficient network selector placement in control plane of multiple networks-on-chip
Multiple networks-on-chip is a popular on-chip interconnect. This parallel communication
infrastructure uses more than one NoCs to facilitate customized traffic distribution. Parallel …
infrastructure uses more than one NoCs to facilitate customized traffic distribution. Parallel …
Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA
S SB, A M. Sandi - International Journal of Pervasive Computing and …, 2022 - emerald.com
Purpose The small area network for data communication within routers is suffering from
storage of packet, throughput, latency and power consumption. There are a lot of solutions to …
storage of packet, throughput, latency and power consumption. There are a lot of solutions to …
A router architecture with dual input and dual output channels for Networks-on-Chip
W Zhou, Y Ouyang, Y Lu, H Liang - Microprocessors and Microsystems, 2022 - Elsevier
Abstract Networks-on-Chip (NoCs) are the most viable and scalable solution for connecting
thousands of processing cores, and are emerging as the interconnect infrastructure for future …
thousands of processing cores, and are emerging as the interconnect infrastructure for future …