A modern primer on processing in memory
Modern computing systems are overwhelmingly designed to move data to computation. This
design choice goes directly against at least three key trends in computing that cause …
design choice goes directly against at least three key trends in computing that cause …
Understanding rowhammer under reduced wordline voltage: An experimental study using real dram devices
RowHammer is a circuit-level DRAM vulnerability, where repeatedly activating and
precharging a DRAM row, and thus alternating the voltage of a row's wordline between low …
precharging a DRAM row, and thus alternating the voltage of a row's wordline between low …
HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
SpyHammer: Using RowHammer to remotely spy on temperature
RowHammer is a DRAM vulnerability that can cause bit errors in a victim DRAM row by just
accessing its neighboring DRAM rows at a high-enough rate. Recent studies demonstrate …
accessing its neighboring DRAM rows at a high-enough rate. Recent studies demonstrate …
DR-STRaNGe: end-to-end system design for DRAM-based true random number generators
Random number generation is an important task in a wide variety of critical applications
including cryptographic algorithms, scientific simulations, and industrial testing tools. True …
including cryptographic algorithms, scientific simulations, and industrial testing tools. True …
FracDRAM: Fractional values in off-the-shelf DRAM
F Gao, G Tziantzioulis… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
As one of the cornerstones of computing, dynamic random-access memory (DRAM) is
prevalent across digital systems. Over the years, researchers have proposed modifications …
prevalent across digital systems. Over the years, researchers have proposed modifications …
A case for self-managing DRAM chips: Improving performance, efficiency, reliability, and security via autonomous in-DRAM maintenance operations
The memory controller is in charge of managing DRAM maintenance operations (eg,
refresh, RowHammer protection, memory scrubbing) in current DRAM chips. Implementing …
refresh, RowHammer protection, memory scrubbing) in current DRAM chips. Implementing …
A case for transparent reliability in DRAM systems
Today's systems have diverse needs that are difficult to address using one-size-fits-all
commodity DRAM. Unfortunately, although system designers can theoretically adapt …
commodity DRAM. Unfortunately, although system designers can theoretically adapt …
A low-cost reduced-latency dram architecture with dynamic reconfiguration of row decoder
F Bai, S Wang, X Jia, Y Guo, B Yu… - … Transactions on Very …, 2022 - ieeexplore.ieee.org
DRAM latency has remained almost constant over decades and has become a performance
bottleneck of computing systems. In this study, we propose a low-cost DRAM architecture …
bottleneck of computing systems. In this study, we propose a low-cost DRAM architecture …
Enabling Effective Error Mitigation in Memory Chips That Use On-Die Error-Correcting Codes
M Patel - arXiv preprint arXiv:2204.10387, 2022 - arxiv.org
Improvements in main memory storage density are primarily driven by process technology
scaling, which negatively impacts reliability by exacerbating various circuit-level error …
scaling, which negatively impacts reliability by exacerbating various circuit-level error …