Demonstration of a nanosheet FET with high thermal conductivity material as buried oxide: Mitigation of self-heating effect
Self-heating-induced thermal degradation is a severe issue in nonplanar MOS architectures.
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …
Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs
We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-
oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive …
oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive …
Trench gate nanosheet FET to suppress leakage current from substrate parasitic channel
KS Lee, BD Yang, JY Park - IEEE Transactions on Electron …, 2023 - ieeexplore.ieee.org
Recently, nanosheet FETs (NS FETs) have been introduced as promising candidates for
beyond 3-nm node technology. However, difficulties remain for mass production of the NS …
beyond 3-nm node technology. However, difficulties remain for mass production of the NS …
NS-GAAFET compact modeling: technological challenges in Sub-3-nm circuit performance
NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future
technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are …
technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are …
Investigation of Source/Drain Recess Engineering and Its Impacts on FinFET and GAA Nanosheet FET at 5 nm Node
D Wang, X Sun, T Liu, K Chen, J Yang, C Wu, M Xu… - Electronics, 2023 - mdpi.com
Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-
all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been …
all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been …
Compact Physics Hot-Carrier Degradation Model Valid over a Wide Bias Range
We develop a compact physics model for hot-carrier degradation (HCD) that is valid over a
wide range of gate and drain voltages (V gs and V ds, respectively). Special attention is paid …
wide range of gate and drain voltages (V gs and V ds, respectively). Special attention is paid …
A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors
J Yang, Z Huang, D Wang, T Liu, X Sun, L Qian, Z Pan… - Micromachines, 2023 - mdpi.com
In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation
(BDI), ie, Full BDI_Last, with integration of a sacrificial Si0. 5Ge0. 5 layer was proposed and …
(BDI), ie, Full BDI_Last, with integration of a sacrificial Si0. 5Ge0. 5 layer was proposed and …
Buried interfacial gate oxide for tri-gate negative-capacitance fin field-effect transistors: approach and investigation
V Chauhan, DP Samajdar - Journal of Physics D: Applied Physics, 2023 - iopscience.iop.org
Negative-capacitance fin field-effect transistors (NC-FinFETs), due to their superior gate
electrostatics and dominance over short channel effects (SCEs), have been a key …
electrostatics and dominance over short channel effects (SCEs), have been a key …
Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications
K Chen, J Yang, C Wu, C Wang, M Xu… - IEEE Access, 2023 - ieeexplore.ieee.org
The application of SiC-based strain-relaxed buffers (SRB) technology in gate-all-around
(GAA) pMOS nanosheet transistors (NS-FETs) fabrication has been systematically …
(GAA) pMOS nanosheet transistors (NS-FETs) fabrication has been systematically …
Impact of Bottom Dielectric Isolation of Si-Stacked Nanosheet Transistor on Stress and Self-Heating at 3-nm Node and Beyond
M Saleh, AM Bayoumi… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
This study examines the effect of leakage current reduction techniques on the performance
of the nanosheet FETs (NS-FETs) at 3 nm and beyond. We study the effects of the …
of the nanosheet FETs (NS-FETs) at 3 nm and beyond. We study the effects of the …