Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis
Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog
operational properties of DRAM circuitry to enable massively parallel in-DRAM computation …
operational properties of DRAM circuitry to enable massively parallel in-DRAM computation …
Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
Read disturbance in modern DRAM chips is a widespread phenomenon and is reliably used
for breaking memory isolation, a fundamental building block for building robust systems …
for breaking memory isolation, a fundamental building block for building robust systems …
{ABACuS}:{All-Bank} Activation Counters for Scalable and Low Overhead {RowHammer} Mitigation
We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation
technique that performance-, energy-, and area-efficiently scales with worsening …
technique that performance-, energy-, and area-efficiently scales with worsening …
[PDF][PDF] Abacus: All-bank activation counters for scalable and low overhead rowhammer mitigation
We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation
technique that performance-, energy-, and area-efficiently scales with worsening …
technique that performance-, energy-, and area-efficiently scales with worsening …
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration
H Du, Y Qin, S Chen, Y Kang - ACM Transactions on Architecture and …, 2024 - dl.acm.org
DRAM memory is a performance bottleneck for many applications, due to its high access
latency. Previous work has mainly focused on data locality, introducing small but fast regions …
latency. Previous work has mainly focused on data locality, introducing small but fast regions …
Amplifying Main Memory-Based Timing Covert and Side Channels using Processing-in-Memory Operations
The adoption of processing-in-memory (PiM) architectures has been gaining momentum
because they provide high performance and low energy consumption by alleviating the data …
because they provide high performance and low energy consumption by alleviating the data …
Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance
We present the first rigorous security, performance, energy, and cost analyses of the state-of-
the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting …
the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting …
Hifi-dram: Enabling high-fidelity dram research by uncovering sense amplifiers with ic imaging
DRAM vendors do not disclose the architecture of the sense amplifiers deployed in their
chips. Unfortunately, this hinders academic research that focuses on studying or improving …
chips. Unfortunately, this hinders academic research that focuses on studying or improving …
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture
A Olgun, FN Bostanci… - ACM Transactions on …, 2024 - dl.acm.org
Modern computing systems access data in main memory at coarse granularity (eg, at 512-bit
cache block granularity). Coarse-grained access leads to wasted energy because the …
cache block granularity). Coarse-grained access leads to wasted energy because the …
SpyHammer: Understanding and Exploiting RowHammer under Fine-Grained Temperature Variations
L Orosa, U Rührmair, AG Yagӏıkçı, H Luo… - IEEE …, 2024 - ieeexplore.ieee.org
RowHammer is a DRAM vulnerability that can cause bit errors in a victim DRAM row solely
by accessing its neighboring DRAM rows at a high-enough rate. Recent studies …
by accessing its neighboring DRAM rows at a high-enough rate. Recent studies …