Implementation of gating technique with modified scan flip-flop for low power testing of VLSI chips
R Jayagowri, KS Gurumurthy - Progress in VLSI Design and Test: 16th …, 2012 - Springer
We present a technique to reduce the power of combinational circuits during testing. Power
dissipation of IC during test mode is greater than the IC's normal mode of functioning. During …
dissipation of IC during test mode is greater than the IC's normal mode of functioning. During …
[PDF][PDF] Techniques for Low Power and Area Optimized VLSI Testing using Novel Scan Flip-Flop
R Jayagowri - International Journal of Computer Applications, 2015 - Citeseer
Power consumption of any circuit is high during test mode than its normal mode of
functioning. Different techniques are proposed to reduce the test power. This paper presents …
functioning. Different techniques are proposed to reduce the test power. This paper presents …