SAT-sweeping enhanced for logic synthesis

L Amarú, F Marranghello, E Testa… - 2020 57th ACM/IEEE …, 2020 - ieeexplore.ieee.org
SAT-sweeping is a powerful method for simplifying logic networks. It consists of merging
gates that are proven equivalent (up to complementation) by running simulation and SAT …

Reducing power with activity trigger analysis

J Lanik, J Legriel, E Piriou, E Viaud… - 2015 ACM/IEEE …, 2015 - ieeexplore.ieee.org
In this paper we propose and implement a methodology for power reduction in digital
circuits, closing the gap between conceptual (by designer) and local (by EDA) clock gating …

Satisfiability sweeping for synthesis

LG Amaru, J Luo, P Vuillod - US Patent 11,120,184, 2021 - Google Patents
A system and method for SAT-sweeping is disclosed. According to one embodiment, a
method includes determining gate classes by inputting simulation patterns to gates in an …

Power reduction in digital circuits

J Láník - 2016 - theses.hal.science
The topic of this thesis are methods for power reduction in digital circuits by reducing
average switching on the transistor level. These methods are structural in the sense that they …

Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms

MAMS Elbayoumi - 2015 - vtechworks.lib.vt.edu
According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This
causes an exponential increase of the available area, and hence, the complexity of modern …

Strategies for Quality and Performance Improvement of Hardware Verification and Synthesis Algorithms

MAMS Elbayoumi - 2014 - search.proquest.com
According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This
causes an exponential increase of the available area, and hence, the complexity of modern …