Ultra-Low Dislocation Ge on Silicon Virtual Substrate: New Insights from Crystal Plasticity Simulations

Abstract

By sintering porous Si/Ge films, researchers were able to create high-quality germanium (Ge) epilayers on silicon (Si) with low threading dislocation density. The experimental procedure involves dislocation-selective electrochemical etching of Si/Ge films to create porous Ge nanostructures. Moreover, the voids layer then traps dislocations and blocks them from spreading to the Ge thin-film surface. Furthermore, a microstructure-based multiple slip crystal plasticity model is used in conjunction with finite element analysis to simulate a representative volume element of the Ge thin-film produced on Si (001) surface, which closely resembles the experimental technique. The evolution of mobile and immobile dislocation density is calculated, and the findings demonstrate a drop in overall dislocation density within the voids spacing region, as well as a reduction in stresses due to dislocation pinning and subsequent annihilation at the voids free surface. Thus, the numerical simulations predict the termination of threading dislocations propagation at the embedded voids layer which agree with the transmission electron microscope (TEM) observations. Threading dislocation density reduction in Ge epitaxial thin-film will subsequently increase carrier’s mobility and life time in semiconductor’s active layer, thus increasing the device efficiency. This study provides a design tool to guide integration of dissimilar materials on silicon.