US6498112B1 - Graded oxide caps on low dielectric constant (low K) chemical vapor deposition (CVD) films - Google Patents
Graded oxide caps on low dielectric constant (low K) chemical vapor deposition (CVD) films Download PDFInfo
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- US6498112B1 US6498112B1 US09/904,943 US90494301A US6498112B1 US 6498112 B1 US6498112 B1 US 6498112B1 US 90494301 A US90494301 A US 90494301A US 6498112 B1 US6498112 B1 US 6498112B1
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- silane
- dielectric layer
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for filling contact openings and vias with copper and creating copper interconnections and lines.
- reducing the size, or scale, of the components of a typical transistor also requires reducing the size and cross-sectional dimensions of electrical interconnects to contacts to active areas, such as N + (P + ) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor, and the like.
- active areas such as N + (P + ) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor, and the like.
- Increased resistance and electromigration are undesirable for a number of reasons. For example, increased resistance may reduce device drive current, and source/drain current through the device, and may also adversely affect the overall speed and operation of the transistor.
- Al interconnects aluminum (Al) interconnects
- electrical currents actually carry Al atoms along with the current, causing them to electromigrate may lead to degradation of the Al interconnects, further increased resistance, and even disconnection and/or delamination of the Al interconnects.
- the ideal interconnect conductor for semiconductor circuitry will be inexpensive, easily patterned, have low resistivity, and high resistance to corrosion, electromigration, and stress migration.
- Aluminum (Al) is most often used for interconnects in contemporary semiconductor fabrication processes primarily because Al is inexpensive and easier to etch than, for example, copper (Cu). However, because Al has poor electromigration characteristics and high susceptibility to stress migration, it is typical to alloy Al with other metals.
- Al has a resistivity of 2.824 ⁇ 10 ⁇ 6 ohms-cm at 20° C.
- silver with a resistivity of 1.59 ⁇ 10 ⁇ 6 ohms-cm (at 20° C.)
- copper (Cu) with a resistivity of 1.73 ⁇ 10 ⁇ 6 ohms-cm (at 20° C.)
- gold with a resistivity of 2.44 ⁇ 10 ⁇ 6 ohms-cm (at 20° C.), fall short in other significant criteria.
- Silver for example, is relatively expensive and corrodes easily, and gold is very costly and difficult to etch.
- Copper with a resistivity nearly on par with silver, immunity from electromigration, high ductility (which provides high immunity to mechanical stresses generated by differential expansion rates of dissimilar materials in a semiconductor chip) and high melting point (1083° C. for Cu vs. 660° C. for Al), fills most criteria admirably.
- Cu is difficult to etch in a semiconductor environment. As a result of the difficulty in etching Cu, an alternative approach to forming vias and metal lines must be used.
- the damascene approach consisting of etching openings such as trenches in the dielectric for lines and vias and creating in-laid metal patterns, is the leading contender for fabrication of sub-0.25 micron (sub-0.25 ⁇ ) design rule Cu-metallized circuits.
- the lower resistance and higher conductivity of the Cu interconnects coupled with higher device density and, hence, decreased distance between the Cu interconnects, may lead to increased capacitance between the Cu interconnects.
- Increased capacitance between the Cu interconnects results in increased RC time delays and longer transient decay times in the semiconductor device circuitry, causing decreased overall operating speeds of the semiconductor devices.
- low dielectric constant or “low K” dielectric materials, where K is less than or equal to about 4, for the interlayer dielectric layers (ILD's) in which the Cu interconnects are formed using the damascene techniques.
- low K dielectric materials are difficult materials to use in conjunction with the damascene techniques.
- some low K dielectric materials are susceptible to being damaged and weakened during the etching and subsequent processing steps used in the damascene techniques.
- the sidewalls of openings such as trenches and/or vias formed in low K dielectric materials are especially vulnerable.
- some low K dielectric materials are porous and are a weak and non-uniform substrate for the deposition of a barrier metal layer.
- porous low K dielectric materials may have open pores (caused in part by air retained in the porous low K dielectric materials), which are undesirable in a substrate on which a barrier metal layer is to be deposited because of outgassing and surface roughness.
- barrier metal layers are typically used to protect material adjacent the copper (Cu) interconnects in the semiconductor devices from being poisoned by copper (Cu) atoms diffusing from the copper (Cu) interconnect into the adjacent material.
- the barrier metal layer(s) may protect adjacent silicon-containing structures from being poisoned by copper (Cu) atoms diffusing from the copper (Cu) interconnect into the adjacent silicon-containing structures.
- a diffusion barrier layer and/or an etch stop layer typically silicon nitride, Si 3 N 4 , or SiN, for short, or amorphous silicon carbide, or some combination SiC x N y H z ) formed above a low K dielectric layer typically does not adhere well.
- the adhesion of a diffusion barrier layer and/or a nitride etch stop layer to an underlying low K dielectric layer needs to be improved.
- PECVD plasma-enhanced chemical vapor deposition
- PECVD plasma-enhanced chemical vapor deposition
- the initiation of the cap deposition process frequently leads to one or more physical and/or chemical changes in the upper portions of the low K dielectric films. These physical and/or chemical changes in the upper portions of the low K dielectric films may adversely affect the physical properties of the interface.
- the adhesion between the low K dielectric film and the cap layer may be decreased, the effective dielectric constant of the low K dielectric film may be increased, increasing the capacitive coupling between neighboring copper lines and hence the RC delay times in the integrated circuit, and/or a current leakage route may be established at such an interface.
- the present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
- a method comprising forming a first dielectric layer above a structure layer, the first dielectric layer having an upper portion.
- the method also comprises grading the upper portion of the first dielectric layer using at least one of monomethyl silane, dimethyl silane, trimethyl silane, and tetramethyl silane with helium (He) and at least one of nitrous oxide (N 2 O) and molecular nitrogen (O 2 ).
- a device comprising a first dielectric layer above a structure layer, the first dielectric layer having an upper portion, wherein the upper portion has been graded using at least one of monomethyl silane, dimethyl silane, trimethyl silane, and tetramethyl silane with helium (He) and at least one of nitrous oxide (N 2 O) and molecular nitrogen (O 2 )BRIEF
- FIGS. 1-12 schematically illustrate a process flow according to various embodiments of the present invention. and, more particularly:
- FIG. 1 schematically illustrates a first dielectric layer formed above a structure layer according to various embodiments of the present invention
- FIG. 2 schematically illustrates grading upper portions of the first dielectric layer by reducing a flow of monomethyl silane; increasing a flow of the helium (He) and increasing a flow of the at least one of nitrous oxide (N 2 O) and molecular nitrogen (O 2 ), according to various embodiments of the present invention;
- FIG. 3 schematically illustrates grading upper portions of the first dielectric layer by reducing a flow of dimethyl silane, increasing a flow of the helium (He) and increasing a flow of the at least one of nitrous oxide (N 2 O) and molecular nitrogen (O 2 ), according to various embodiments of the present invention
- FIG. 4 schematically illustrates grading upper portions of the first dielectric layer by reducing a flow of trimethyl silane, increasing a flow of the helium (He) and increasing a flow of the at least one of nitrous oxide (N 2 O) and molecular nitrogen (O 2 ), according to various embodiments of the present invention
- FIG. 5 schematically illustrates grading upper portions of the first dielectric layer by reducing a flow of tetramethyl silane, increasing a flow of the helium (He) and increasing a flow of the at least one of nitrous oxide (N 2 O) and molecular nitrogen (O 2 ), according to various embodiments of the present invention
- FIG. 6 schematically illustrates upper portions of the graded first dielectric layer following the grading, according to various alternative embodiments of the present invention
- FIG. 7 schematically illustrates an opening formed in the graded first dielectric layer according to various embodiments of the present invention.
- FIG. 8 schematically illustrates a barrier metal layer formed in the opening and above the first dielectric layer according to various embodiments of the present invention
- FIG. 9 schematically illustrates a copper seed layer formed adjacent the barrier metal layer according to various embodiments of the present invention.
- FIG. 10 schematically illustrates a copper layer formed adjacent the copper seed layer according to various embodiments of the present invention.
- FIG. 11 schematically illustrates planarization of the copper layer and removal of the copper layer, copper seed layer and barrier metal layer outside of the opening according to various embodiments of the present invention.
- FIG. 12 schematically illustrates a second dielectric layer formed above the first dielectric layer and the copper structure according to various embodiments of the present invention.
- FIGS. 1-12 Illustrative embodiments of a method for semiconductor device fabrication according to the present invention are shown in FIGS. 1-12.
- FIGS. 1-12 Illustrative embodiments of a method for semiconductor device fabrication according to the present invention are shown in FIGS. 1-12.
- the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Nevertheless, the attached drawings are included to provide illustrative examples of the present invention.
- the present invention is directed towards the manufacture of a semiconductor device.
- the present method is applicable to a variety of technologies, for example, NMOS, PMOS, CMOS, and the like, and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, and the like.
- a first dielectric layer 105 may be formed above a structure layer 100 such as a semiconducting substrate.
- a structure layer 100 such as a semiconducting substrate.
- the present invention is not limited to the formation of a portion of a copper-based interconnect above the surface of a semiconducting substrate such as a silicon wafer, for example. Rather, as will be apparent to one skilled in the art upon a complete reading of the present disclosure, a copper-based interconnect formed in accordance with the present invention may be formed above previously formed semiconductor devices and/or process layer, e.g., transistors, or other similar structure. In effect, the present invention may be used to form process layers on top of previously formed process layers.
- the structure layer 100 may be an underlayer of semiconducting material, such as a silicon substrate or wafer, or, alternatively, may be an underlayer of semiconductor devices, such as a layer of metal oxide semiconductor field effect transistors (MOSFETs), and the like, and/or a metal interconnection layer or layers and/or an interlayer dielectric (ILD) layer or layers, and the like.
- MOSFETs metal oxide semiconductor field effect transistors
- ILD interlayer dielectric
- the first dielectric layer 105 is formed above the structure layer 100 .
- the first dielectric layer 105 may be formed from a variety of “low dielectric constant” or “low K” (K is less than or equal to about 4) dielectric materials.
- the low K first dielectric layer 105 may be formed by a variety of known techniques for forming such layers, e.g., chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), spin-on glass, and the like, and may have a thickness ranging from approximately 2000 ⁇ -10000 ⁇ , for example.
- the low K first dielectric layer 105 may be formed from a variety of low K dielectric materials, where K is less than or equal to about 4. Examples include organosilicate glass (OSG) materials such as Applied Material's Black Diamond®, Novellus' Coral®, Allied Signal's Nanoglass®, JSR's LKD, and the like. In one illustrative embodiment, the low K first dielectric layer 105 is comprised of Applied Material's Black Diamond®, having a thickness of approximately 5000 ⁇ , formed by being blanket-deposited by a plasma-enhanced chemical vapor deposition (PECVD).
- PECVD plasma-enhanced chemical vapor deposition
- upper portions 210 , 310 , 410 and 510 of the first dielectric layer 105 may be graded using at least one of monomethyl silane (SiH 3 (CH 3 )), dimethyl silane (SiH 2 (CH 3 ) 2 ), trimethyl silane (SiH(CH 3 ) 3 ), or tetramethyl silane (Si(CH 3 ) 4 ), respectively, with helium (He) and at least one of nitrous oxide (N 2 O) and/or molecular oxygen (O 2 ).
- SiH 3 (CH 3 ) monomethyl silane
- dimethyl silane SiH 2 (CH 3 ) 2
- trimethyl silane SiH(CH 3 ) 3
- tetramethyl silane Si(CH 3 ) 4
- the grading of the upper portions 210 , 310 , 410 and 510 of the first dielectric layer 105 may comprise reducing the flow of the monomethyl silane (SiH 3 (CH 3 )), the dimethyl silane (SiH 2 (CH 3 ) 2 ), the trimethyl silane (SiH(CH 3 ) 3 ), and/or the tetramethyl silane (Si(CH 3 ) 4 ), increasing the flow of the helium (He), and increasing the flow of the nitrous oxide (N 2 O) and/or the molecular oxygen (O 2 ).
- the deposition conditions may be gradually changed from those used to form a low K carbon-containing film to those used to form a standard oxide layer having substantially no carbon (C).
- This transition may be accomplished by stages to form a graded transition from the low K carbon-containing film to the standard oxide layer having substantially no carbon (C).
- the grading of the graded transition may involve lowering the flow of the precursor such as monomethyl silane (SiH 3 (CH 3 )), dimethyl silane (SiH 2 (CH 3 ) 2 ), trimethyl silane (SiH(CH 3 ) 3 ), or tetramethyl silane (Si(CH 3 ) 4 ), raising the flow of an oxidant such as nitrous oxide (N 2 O) and/or molecular oxygen (O 2 ), and raising the flow of some helium (He).
- the precursor such as monomethyl silane (SiH 3 (CH 3 )
- dimethyl silane SiH 2 (CH 3 ) 2
- trimethyl silane SiH(CH 3 ) 3
- tetramethyl silane Si(CH 3 ) 4
- raising the flow of an oxidant such as nitrous oxide (N 2 O) and/
- the upper portion 210 of the first dielectric layer 105 may be graded using monomethyl silane (SiH 3 (CH 3 )), with helium (He) and at least one of nitrous oxide (N 2 O) and/or molecular oxygen (O 2 ), as indicated schematically by the arrows 200 .
- the grading of the upper portion 210 of the first dielectric layer 105 comprises reducing the flow of the monomethyl silane (SiH 3 (CH 3 )), increasing the flow of the helium (He), and increasing the flow of the nitrous oxide (N 2 O) and/or the molecular oxygen (O 2 ).
- the upper portion 210 is bounded above, by an upper surface 220 , and below, as shown by phantom line 230 .
- the upper portion 210 of the first dielectric layer 105 may have a thickness t d1 in a range of about 100-1000 ⁇ , for example.
- the upper portion 310 of the first dielectric layer 105 may be graded using dimethyl silane (SiH 2 (CH 3 ) 2 ), with helium (He) and at least one of nitrous oxide (N 2 O) and/or molecular oxygen (O 2 ), as indicated schematically by the arrows 300 .
- the grading of the upper portion 310 of the first dielectric layer 105 comprises reducing the flow of the dimethyl silane (SiH 2 (CH 3 ) 2 ), increasing the flow of the helium (He), and increasing the flow of the nitrous oxide (N 2 O) and/or the molecular oxygen (O 2 ).
- the upper portion 310 is bounded above, by an upper surface 320 , and below, as shown by phantom line 330 .
- the upper portion 310 of the first dielectric layer 105 may have a thickness t d1 in a range of about 100-1000 ⁇ , for example.
- the upper portion 410 of the first dielectric layer 105 may be graded using trimethyl silane (SiH(CH 3 ) 3 ), with helium (He) and at least one of nitrous oxide (N 2 O) and/or molecular oxygen (O 2 ), as indicated schematically by the arrows 400 .
- the grading of the upper portion 410 of the first dielectric layer 105 comprises reducing the flow of the trimethyl silane (SiH(CH 3 ) 3 ), increasing the flow of the helium (He), and increasing the flow of the nitrous oxide (N 2 O) and/or the molecular oxygen (O 2 ).
- the upper portion 410 is bounded above, by an upper surface 420 , and below, as shown by phantom line 430 .
- the upper portion 410 of the first dielectric layer 105 may have a thickness t d1 in a range of about 100-1000 ⁇ , for example.
- the upper portion 510 of the first dielectric layer 105 may be graded using tetramethyl silane (Si(CH 3 ) 4 ), with helium (He) and at least one of nitrous oxide (N 2 O) and/or molecular oxygen (O 2 ), as indicated schematically by the arrows 500 .
- the grading of the upper portion 510 of the first dielectric layer 105 comprises reducing the flow of the tetramethyl silane (Si(CH 3 ) 4 ), increasing the flow of the helium (He), and increasing the flow of the nitrous oxide (N 2 O) and/or the molecular oxygen (O 2 ).
- the upper portion 510 is bounded above, by an upper surface 520 , and below, as shown by phantom line 530 .
- the upper portion 510 of the first dielectric layer 105 may have a thickness t d1 in a range of about 100-1000 ⁇ , for example.
- FIG. 6 schematically illustrates upper portions of the graded first dielectric layer following the grading, according to various alternative embodiments of the present invention
- the upper portion 210 of the first dielectric layer 105 is schematically illustrated following the grading as described above.
- the graded upper portion 210 has a graded transition from a lower carbon-containing portion 630 , substantially adjacent the phantom line 230 , to an upper oxide portion 620 , substantially adjacent the upper surface 220 , having substantially no carbon (C).
- an opening 700 is formed in the first dielectric layer 105 .
- the opening 700 may be formed for conductive metal lines, contact holes, via holes, and the like, and may be etched into the first dielectric layer 105 .
- the opening 700 may have a width w that may be in a range of about 1000-5000 ⁇ , for example.
- the opening 700 may be formed by using a variety of known anisotropic etching techniques, such as a reactive ion etching (RIE) process using hydrogen bromide (HBr) and argon (Ar) as the etchant gases, for example.
- RIE reactive ion etching
- RIE reactive ion etching
- CHF 3 trifluoromethane or fluoroform
- Ar argon
- Plasma etching may also be used in various illustrative embodiments.
- a thin barrier metal layer of tantalum (Ta) 800 and a copper (Cu) seed layer 900 are applied to the entire surface using vapor-phase deposition.
- the barrier metal layer 800 and the copper (Cu) seed layer 900 blanket-deposit the first dielectric layer 105 and the opening 700 .
- the barrier metal layer 800 may be formed of at least one layer of a barrier metal material, such as tantalum or tantalum nitride, and the like.
- the barrier metal layer 800 may also be formed of titanium nitride, titanium-tungsten, nitrided titanium-tungsten, magnesium, or another suitable barrier material.
- the copper seed layer 900 may be formed on top of the one or more barrier metal layers 800 by physical vapor deposition (PVD) or chemical vapor deposition (CVD), for example.
- the bulk of the copper trench-fill (or trench-fill of another conductive material) is frequently done using an electroplating technique, where the conductive surface comprising the one or more barrier metal layers 800 and the copper seed layer 900 may be mechanically clamped to an electrode (not shown) to establish an electrical contact, and the structure layer 100 is then immersed in an electrolyte solution containing copper (Cu) ions (or ions of another conductive material).
- An electrical current is then passed through the wafer-electrolyte system to cause reduction and deposition of copper (Cu) atoms (or atoms of another conductive material) on the copper seed layer 900 .
- an alternating-current bias of the wafer-electrolyte system has been considered as a method of self-planarizing the deposited copper (Cu) film (or film of another conductive material), similar to the deposit-etch cycling used in high-density plasma (HDP) tetraethyl orthosilicate (TEOS) dielectric depositions.
- HDP high-density plasma
- TEOS tetraethyl orthosilicate
- this process typically produces a planar coating of copper (Cu) 1000 (or another conductive material) of substantially constant thickness above the first dielectric layer 105 , being thicker, of course, where the opening 700 (FIGS. 7-4) had been.
- the layer of copper (Cu) 1000 may be planarized using chemical mechanical planarization (CMP) techniques.
- the planarization using chemical mechanical planarization (CMP) clears all copper (Cu) and barrier metal from above the first dielectric layer 105 , leaving a copper (Cu) structure 1100 , such as a copper-filled via and/or trench, forming a portion of a copper-interconnect, adjacent remaining portions 1130 and 1140 of the one or more barrier metal layers 800 and copper seed layer 900 , respectively, as shown in FIG. 11 .
- CMP chemical mechanical planarization
- a second dielectric layer 1200 is formed above the first dielectric layer 105 and above the copper (Cu) structure 1100 .
- the second dielectric layer 1200 may be a diffusion barrier layer and/or an etch stop layer (typically formed of silicon nitride, Si 3 N 4 , or SiN, for short).
- the second dielectric layer 1200 may be formed by a variety of known techniques for forming such layers, e.g., chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and the like, and may have a thickness ranging from approximately 100 ⁇ -1000 ⁇ , for example.
- any of the above-disclosed embodiments of a method of forming a portion of a copper interconnect enables a copper interconnect to be formed using conventional damascene techniques in conjunction with treated low K dielectric materials that are far more robust than the conventional low K materials typically used in conventional damascene techniques.
- a treated low K dielectric layer adjacent the copper interconnect all of the advantages of using a low K dielectric layer to reduce the capacitance and RC delays between adjacent copper interconnects are retained, without any of the difficulties of forming the copper interconnect using a conventional untreated low K dielectric during the conventional damascene processing.
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Abstract
Description
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US09/904,943 US6498112B1 (en) | 2001-07-13 | 2001-07-13 | Graded oxide caps on low dielectric constant (low K) chemical vapor deposition (CVD) films |
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US09/904,943 US6498112B1 (en) | 2001-07-13 | 2001-07-13 | Graded oxide caps on low dielectric constant (low K) chemical vapor deposition (CVD) films |
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