Sum of absolute differences (SAD) calculation is one of the most time-consuming operations
of video encoders compatible with the high efficiency video coding standard. SAD hardware …

This paper presents the algorithm and the architecture of the high-throughput motion
estimation system for the H. 265/HEVC encoder. The design allows the processing of …

In this paper, approximate Versatile Video Coding (VVC) fractional interpolation filters are
proposed. They significantly reduce computational complexity of VVC fractional interpolation …

Fractional interpolation in Versatile Video Coding (VVC) standard has much higher
computational complexity than fractional interpolation in previous video compression …

Sub-pixel interpolation is one of the most computationally intensive parts of High Efficiency
Video Coding (HEVC) video encoder and decoder. Therefore, in this paper, a low energy …

This paper presents an energy-aware and high-throughput hardware design for the
Fractional Motion Estimation (FME) compliant with the High Efficiency Video Coding (HEVC) …

We present a novel reconfigurable hardware architecture for interpolation filtering in high
efficient video coding that adapts to run-time changes of the number of interpolation filter …

This paper provides a comprehensive analysis of the computational complexity, power
consumption, temperature, and memory access behavior for the next-generation High …

High efficiency video coding (HEVC) fractional interpolation algorithm has very high
computational complexity. In this paper, two approximate HEVC fractional interpolation filters …

This paper presents the architecture of the high-throughput compensator and the
interpolator used in the motion estimation of the H. 265/HEVC encoder. The architecture can …