Finding new materials for copper/low-k interconnects is critical to the continuing
development of computer chips. While copper/low-k interconnects have served well …

Chip-packaging interaction is becoming a critical reliability issue for Cu/low k chips during
package assembly. With the traditional TEOS interlevel dielectric being replaced by much …

An interconnect structure and a method for forming the same are described. Specifically,
under the present invention, a gouge is created within a via formed in the interconnect …

An interconnect structure including a gouging feature at the bottom of one of the via
openings and a method of forming the same are provided. In accordance with the present …

Ultra low-k (ULK, k= 2.4) dielectric has weaker mechanical properties than first generation
low-k films (k= 3.0). The introduction of ULK into advanced back end of lines (BEOL) …

Chip-package-interaction (CPI) induced BEoL (back-end-of-line) delamination has emerged
as a major reliability concern with the adoption of Cu/low-k as the mainstream BEoL …

Methods are provided that enable the ability to use a less aggressive liner processes, while
producing structures known to give a desired high stress migration and electro-migration …

We present a finite element based analysis to determine if thermally induced stresses in
inter-wafer Cu via structures in 3D ICs using BCB-bonded wafers is a potential reliability …

Thin film characterization, electrical performance, and preliminary reliability of physical
vapor-deposited (PVD) TaN/chemical vapor-deposited (CVD) Ru bilayer were carried out to …

Copper diffusion barrier properties of phosphorous doped Ru film are studied. Phosphorous
out-diffusion to Ru from underneath phosphosilicate glass (PSG) layer results in P doped Ru …