Scaling challenges for advanced CMOS devices
The economic health of the semiconductor industry requires substantial scaling of chip
power, performance, and area with every new technology node that is ramped into …
power, performance, and area with every new technology node that is ramped into …
Single and double diffusion breaks on integrated circuit products comprised of FinFET devices
One illustrative integrated circuit product disclosed herein includes, among other things, a
plurality of FinFET devices, each of which comprises a gate structure comprising a high-k …
plurality of FinFET devices, each of which comprises a gate structure comprising a high-k …
Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices
W Zhao, H Wang, H Shen, Z Hu, MH Chi - US Patent 9,653,583, 2017 - Google Patents
One illustrative method disclosed herein includes, among other things, forming a first gate
structure above a fin, forming epi semiconductor material on the fin, performing at least one …
structure above a fin, forming epi semiconductor material on the fin, performing at least one …
Concealing-gate: Optical contactless probing resilient design
Optical probing, though developed as silicon debugging tools from the chip backside, has
shown its capability of extracting secret data, such as cryptographic keys and user …
shown its capability of extracting secret data, such as cryptographic keys and user …
Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices
A method includes forming a plurality of fins above a substrate. A plurality of gate structures
is formed above the plurality of fins. A first mask layer is formed above the plurality of fins …
is formed above the plurality of fins. A first mask layer is formed above the plurality of fins …
Fin cut enabling single diffusion breaks
H Jagannathan, SK Kanakasabapathy… - US Patent …, 2017 - Google Patents
BACKGROUND The present disclosure relates to the electrical, electronic, and computer
arts, and, more particularly, to methods for cutting fins in the fabrication of integrated circuits …
arts, and, more particularly, to methods for cutting fins in the fabrication of integrated circuits …
Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same
The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB)
abutting end isolation regions, and methods of forming the same. An IC structure may …
abutting end isolation regions, and methods of forming the same. An IC structure may …
Enhanced optimal multi-row detailed placement for neighbor diffusion effect mitigation in sub-10 nm VLSI
Layout-dependent effect causes variation in device performance as well as mismatch in
model-hardware correlation in sub-10 nm nodes. In order to effectively explore the power …
model-hardware correlation in sub-10 nm nodes. In order to effectively explore the power …
Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI
In sub-10nm, nodes, a change or step in diffusion height between adjacent standard cells
causes yield loss as well as a form of model-hardware miscorrelation called neighbor …
causes yield loss as well as a form of model-hardware miscorrelation called neighbor …
Semiconductor device and method for fabricating the same
CK Hsu, SI Fu, CY Chiu, CT Wu, CH Chen… - US Patent …, 2020 - Google Patents
(57) ABSTRACT A method for fabricating semiconductor device includes the steps of:
providing a substrate having a fin-shaped structure thereon; forming a single diffusion break …
providing a substrate having a fin-shaped structure thereon; forming a single diffusion break …