Device requirements for optical interconnects to silicon chips
DAB Miller - Proceedings of the IEEE, 2009 - ieeexplore.ieee.org
We examine the current performance and future demands of interconnects to and on silicon
chips. We compare electrical and optical interconnects and project the requirements for …
chips. We compare electrical and optical interconnects and project the requirements for …
Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review
F Yuan, AR AL‐Taee, A Ye… - IET Circuits, Devices & …, 2014 - Wiley Online Library
This study provides a comprehensive review of decision feedback equalisation (DFE) for
multi‐giga‐bit‐per‐second (Gbps) data links. The state‐of‐the‐art of DFE for multi‐Gbps …
multi‐giga‐bit‐per‐second (Gbps) data links. The state‐of‐the‐art of DFE for multi‐Gbps …
A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology
TO Dickson, JF Bulzacchelli… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
The design and experimental results of a low-power, low-area 5-tap decision feedback
equalizer (DFE) implemented in a 45 nm SOI CMOS technology are reported. The DFE …
equalizer (DFE) implemented in a 45 nm SOI CMOS technology are reported. The DFE …
A 60-Gb/s PAM4 wireline receiver with 2-tap direct decision feedback equalization employing track-and-regenerate slicers in 28-nm CMOS
KC Chen, WWT Kuo, A Emami - IEEE Journal of Solid-State …, 2020 - ieeexplore.ieee.org
This article describes a 4-level pulse amplitude modulation (PAM4) receiver incorporating
continuous time linear equalizers (CTLEs) and a 2-tap direct decision feedback equalizer …
continuous time linear equalizers (CTLEs) and a 2-tap direct decision feedback equalizer …
Power optimized ADC-based serial link receiver
EH Chen, R Yousry, CKK Yang - IEEE Journal of Solid-State …, 2012 - ieeexplore.ieee.org
Implementing serial I/O receivers based on analog-to-digital converters (ADCs) and digital
signal post-processing has drawn growing interest with technology scaling, but power …
signal post-processing has drawn growing interest with technology scaling, but power …
A 25 Gb/s 5.8 mW CMOS equalizer
JW Jung, B Razavi - IEEE Journal of solid-state circuits, 2014 - ieeexplore.ieee.org
Low-power equalization remains in high demand for wireline receivers operating at tens of
gigabits per second in copper media. This paper presents a design incorporating a …
gigabits per second in copper media. This paper presents a design incorporating a …
A 56-Gbps PAM-4 wireline receiver with 4-tap direct DFE employing dynamic CML comparators in 65 nm CMOS
D Wang, Z Wang, H Xu, J Wang, Z Zhao… - … on Circuits and …, 2021 - ieeexplore.ieee.org
This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that
incorporates a continuous time linear equalizer, a variable gain amplifier, a phase …
incorporates a continuous time linear equalizer, a variable gain amplifier, a phase …
Design techniques for a 66 Gb/s 46 mW 3-tap decision feedback equalizer in 65 nm CMOS
This paper analyzes and describes design techniques enabling energy-efficient multi-tap
decision feedback equalizers operated at or near the speed limits of the technology. We …
decision feedback equalizers operated at or near the speed limits of the technology. We …
A 25 Gb/s 1.13 pJ/b− 10.8 dBm input sensitivity optical receiver in 40 nm CMOS
SH Huang, WZ Chen - IEEE Journal of Solid-State Circuits, 2017 - ieeexplore.ieee.org
This paper describes the design of a 25 Gb/s energy-efficient CMOS optical receiver with
high input sensitivity. By incorporating a current-boosting preamplifier with a dual-path time …
high input sensitivity. By incorporating a current-boosting preamplifier with a dual-path time …
A 2.3-mW, 5-Gb/s low-power decision-feedback equalizer receiver front-end and its two-step, minimum bit-error-rate adaptation algorithm
S Son, HS Kim, MJ Park, K Kim… - IEEE journal of solid …, 2013 - ieeexplore.ieee.org
This paper presents a low-power decision-feedback equalizer (DFE) receiver front-end and
a two-step minimum bit-error-rate (BER) adaptation algorithm. A high energy efficiency of …
a two-step minimum bit-error-rate (BER) adaptation algorithm. A high energy efficiency of …