An integrated circuit device comprising a memory cell array having a plurality of memory
cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory …

(*) Notice: Subject to any disclaimer, the term of this “Memory Design Using a One-Transistor
GainCell on SOI, IEEE patent is extended or adjusted under 35 J 1 of Soli ournal of Solid …

US PATENT DOCUMENTS 3.439, 214. A 4, 1969 Kabell 3,997,799 A 12, 1976 Baker
4,032.947 A 6, 1977 Kesel et al. 4,250,569 A 2, 1981 Sasaki et al. 4,262,340 A 4, 1981 …

Techniques for providing floating body memory devices are disclosed. In one particular
exemplary embodiment, the tech niques may be realized as a semiconductor device …

Techniques for reducing a voltage swing are disclosed. In one particular exemplary
embodiment, the techniques may be realized as an apparatus for reducing a voltage swing …

5,144,390 5,164,805 5,258,635 5,313.432 5,315,541 5,350,938 5,355.330 5,388,068
5,397,726 5.432, 730 5,446.299 5.448, 513 5,466,625 5,489,792 5,506.436 5,515,383 …

Techniques for simultaneously driving a plurality of Source lines are disclosed. In one
particular exemplary embodiment, the techniques may be realized as an apparatus for …

An integrated circuit device (for example, a logic device or a memory device (such as, a
discrete memory device)), including a memory cell array having a plurality of memory cells …

(57) ABSTRACT A semiconductor storage device according to one embodi ment of the
present invention, comprising: FBCs (Floating Body Cells) which store data by accumulating …

Techniques for providing a semiconductor memory device are disclosed. In one particular
embodiment, the techniques may be realized as a semiconductor memory device including …