A 40 Gb/s serial link transceiver in 28 nm CMOS technology
A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized
for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit …
for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit …
Silicon photonic microring links for high-bandwidth-density, low-power chip I/O
Silicon photonic microrings have drawn interest in recent years as potential building blocks
for high-bandwidth off-chip communication links. The authors analyze a terabit-per-second …
for high-bandwidth off-chip communication links. The authors analyze a terabit-per-second …
Power optimized ADC-based serial link receiver
EH Chen, R Yousry, CKK Yang - IEEE Journal of Solid-State …, 2012 - ieeexplore.ieee.org
Implementing serial I/O receivers based on analog-to-digital converters (ADCs) and digital
signal post-processing has drawn growing interest with technology scaling, but power …
signal post-processing has drawn growing interest with technology scaling, but power …
A 25 Gb/s 5.8 mW CMOS equalizer
JW Jung, B Razavi - IEEE Journal of solid-state circuits, 2014 - ieeexplore.ieee.org
Low-power equalization remains in high demand for wireline receivers operating at tens of
gigabits per second in copper media. This paper presents a design incorporating a …
gigabits per second in copper media. This paper presents a design incorporating a …
A 21-Gbit/s 1.63-pJ/bit adaptive CTLE and one-tap DFE with single loop spectrum balancing method
This brief presents an adaptive continuous-time linear equalizer (CTLE) and one-tap
decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB …
decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB …
Design techniques for a 66 Gb/s 46 mW 3-tap decision feedback equalizer in 65 nm CMOS
This paper analyzes and describes design techniques enabling energy-efficient multi-tap
decision feedback equalizers operated at or near the speed limits of the technology. We …
decision feedback equalizers operated at or near the speed limits of the technology. We …
Design techniques for a 60 Gb/s 173 mW wireline receiver frontend in 65 nm CMOS technology
Design techniques for a complete 60 Gb/s receiver frontend with equalization, output
slicing/demultiplexing, and clocking capabilities are described. Current integration …
slicing/demultiplexing, and clocking capabilities are described. Current integration …
A 15-Gb/s 0.5-mW/Gbps two-tap DFE receiver with far-end crosstalk cancellation
MH Nazari, A Emami-Neyestanak - IEEE journal of solid-state …, 2012 - ieeexplore.ieee.org
This paper presents a low-power receiver with two-tap decision feedback equalization (DFE)
and novel far-end crosstalk (FEXT) cancellation capability, implemented in a 45-nm SOI …
and novel far-end crosstalk (FEXT) cancellation capability, implemented in a 45-nm SOI …
A 0.31-pJ/bit 20-Gb/s DFE with 1 discrete tap and 2 IIR filters feedback in 40-nm-LP CMOS
KY Chen, WY Chen, SI Liu - … on Circuits and Systems II: Express …, 2016 - ieeexplore.ieee.org
This brief presents a low-power 20-Gb/s decision feedback equalizer (DFE) with one
discrete tap and two infinite impulse response (IIR) filters feedback. The advantage of the IIR …
discrete tap and two infinite impulse response (IIR) filters feedback. The advantage of the IIR …
A 30-Gb/s 1.37-pJ/b CMOS receiver for optical interconnects
This paper presents a digitally controlled 1-V 30-Gb/s 1.37-pJ/b optical receiver in 65-nm
CMOS technology. This receiver consists of an inverter-based inductive transimpedance …
CMOS technology. This receiver consists of an inverter-based inductive transimpedance …