A single-loop referenceless clock and data recovery (CDR) with a compact frequency
acquisition scheme is presented. A bang-bang phase-frequency detector (BBPFD) is …

An 8.2 Gb/s-to-10.3 Gb/s full-rate referenceless CDR in 0.18 μm CMOS is presented. By
realizing an asymmetric phase detector transfer curve, the linear CDR's “single-sided” …

This paper proposes a half-rate single-loop reference-less binary CDR that operates from
8.5 Gb/s to 12.1 Gb/s (36% capture range). The high capture range is made possible by …

Hardware developments have been a major vehicle in popularizing the applications of
signal processing theory in both science and engineering. The book describes the important …

An 8.5-11.5-Gbps SONET transceiver with referenceless clock and data recovery (CDR)
employing an algorithmic frequency acquisition scheme is presented. Without any training …

A 0.25-mum CMOS, multi-rate clock and data recovery (CDR) circuit that leverages unique
analog/digital boundaries in its phase detector and loop filter to achieve a fully integrated …

This brief presents a design of fast frequency locking 320 Mb/s to 2.7 Gb/s continuous-rate
reference-less clock and data recovery (CDR) circuit. A simultaneous coarse/fine frequency …

On-chip jitter measurement can be used to optimize the performance of wireline
transceivers. In this work, the jitter of random data is measured on-chip by correlating the …

A novel clock and data recovery architecture with adaptive loop gain is proposed for spread
spectrum SerDes (serializer/deserializer) applications such as serial AT attachment. The …

(57) ABSTRACT A phase detector, including a sampling device, a comparing device, and an
output device, is provided. The sampling device samples a data signal according to a …