Characterization of V2O5-TiO2 Eurocat catalysts by vibrational and electronic spectroscopies

G Busca, A Zecchina - Catalysis today, 1994 - Elsevier
IR and Raman spectroscopic studies show that the catalyst EL10V1 consists of a
'monolayer'of surface vanadyl complexes spread on the TiO 2 support surface. Such a …

Study on Voltage Influence on FPGA-Based Time-to-Digital Converters

X Xu, Y Wang - 2023 IEEE International Instrumentation and …, 2023 - ieeexplore.ieee.org
Field programmable gate arrays (FPGAs) based time-to-digital converters (TDCs) have been
broadly investigated and widely used in recent years. However, voltage variations on the …

A simple way for substrate noise modeling in mixed-signal ICs

O Valorge, C Andrei, F Calmon… - … on Circuits and …, 2006 - ieeexplore.ieee.org
Here is a complete methodology of substrate noise modeling. The aim of this study is to
predict the perturbations induced by digital commutations flowing through the substrate to …

Built-in sensor for signal integrity faults in digital interconnect signals

V Champac, V Avendaño… - IEEE transactions on very …, 2009 - ieeexplore.ieee.org
Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment
test resources at the multigigahertz range, normally not available. Furthermore, for most …

Mixed-signal IC design guide to enhance substrate noise immunity in bulk silicon technology

O Valorge, F Calmon, C Andrei, C Gontrand… - … Integrated Circuits and …, 2010 - Springer
Predicting substrate cross-talks in mixed-signal circuits has become a critical issue to
preserve signal integrity in future integrated systems. Phenomena that involve substrate …

Predictive high frequency effects of substrate coupling in 3D integrated circuits stacking

E Eid, T Lacrevaz, S de Rivaz… - … Conference on 3D …, 2009 - ieeexplore.ieee.org
In 3D integrated circuits, substrate coupling effects due to propagation of high frequency
(HF) parasitic signals are carried by through silicon vias (TSV). These electrical coupling …

Effective BIST for crosstalk faults in interconnects

T Rudnicki, T Garbolino, K Gucwa… - … Symposium on Design …, 2009 - ieeexplore.ieee.org
The paper is devoted to a test-per-clock method of an at-speed testing of crosstalk faults in
long interconnects between cores in systems-on-a-Chip. A linear feedback shift register …

Design, analysis and test of high-frequency interconnections in 2.5 D package with silicon interposer

X Ren, C Pang, Z Qin, Y Ping, F Jiang… - Journal of …, 2016 - iopscience.iop.org
An interposer test vehicle with TSVs (through-silicon vias) and two redistribute layers (RDLs)
on the top side for 2.5 D integration was fabricated and high-frequency interconnections …

[PDF][PDF] Signal integrity verification using high speed monitors

V Avendano, V Champac, J Figueras - Proceedings. Ninth IEEE …, 2004 - academia.edu
Signal integrity verification is becoming an impor-tant issue as technological process
features continues to shrink and logic speed increases. Advanced technologies permit a …

Effect of simultaneous switching noise on an analog filter

E Backenius, M Vesterbacka… - 2006 13th IEEE …, 2006 - ieeexplore.ieee.org
In this work a digital filter is placed on the same chip as an analog filter. We investigate how
the simultaneous switching noise is propagated from the digital filter to different nodes on a …