This paper presents CMP Cooperative Caching, a unified framework to manage a CMP's
aggregate on-chip cache resources. Cooperative caching combines the strengths of private …

This paper is motivated by the difficulty in writing correct high-performance programs. Writing
shared-memory multi-threaded programs imposes a complex trade-off between …

Many future shared-memory multiprocessor servers will both target commercial workloads
and use highly-integrated" glueless" designs. Implementing low-latency cache coherence in …

Hardware Transactional Memory (HTM) systems reflect choices from three key design
dimensions: conflict detection, version management, and conflict resolution. Previously …

Communication in cache-coherent distributed shared memory (DSM) often requires
invalidating (or writing back) cached copies of a memory block, incurring high overheads …

Since the 1970's, microprocessor-based digital platforms have been riding Moore's law,
allowing for doubling of density for the same area roughly every two years. However …

Recent research suggests that there are large variations in a cache's spatial usage, both
within and across programs. Unfortunately, conventional caches typically employ fixed …

Destination-set prediction can improve the latency/bandwidth tradeoff in shared-memory
multiprocessors. The destination set is the collection of processors that receive a particular …

Techniques are provided for managing caches in a system with multiple caches that may
contain different copies of the same data item. Specifically, techniques are provided for …

The SARC project seeks to improve power scalability of shared-memory chip
multiprocessors (CMPs) by making directory coherence more efficient in both power and …