Experimental evaluation of clustering techniques for component recovery is necessary in
order to analyze their strengths and weaknesses in comparison to other techniques. For …

In this paper, a novel master-slave flip-flop is designed that incorporates 15 transistors and a
single-phase clock, employing topological and adaptive coupling methods. The proposed …

This paper enumerates new architecture of low power dual-edge triggered Flip-Flop
(DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be …

Abstract Background D Flip-Flop as a digital circuit can be used as a timing element in many
sophisticated circuits. Therefore the optimum performance with the lowest power …

A novel master-slave flip-flop is designed using 18 transistors by topological techniques.
The proposed flip-flop circuit (PFC) is compared with the existing flip-flops. Key parameters …

The Transmission Gate FlipFlop (TGFF) is one of the most commonly used flipflops in
circuits. In this paper, we aim to create a low power version of TGFF. A static and then two …

In this paper a low-power double-edge triggered static flip-flop (DETSFF) suitable for low-
power and high performance applications is presented. The designed DETFF is verified at …

In the present era, as the technology becomes more advanced so the demand for low power
and lesser delay devices has increased. So keeping that in mind this paper has presented …

Multi-supply voltage design using Cluster Voltage Scaling (CVS) is an effective way to
reduce power consumption without performance degradation. One of the major issues in this …

In VLSI circuit power reduction is of major concern. Considerable research is carried out in
literature to develop techniques to reduce both dynamic power and leakage power …