Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator

JJ Zhang, T Gu, K Basu, S Garg - 2018 IEEE 36th VLSI Test …, 2018 - ieeexplore.ieee.org
Due to their growing popularity and computational cost, deep neural networks (DNNs) are
being targeted for hardware acceleration. A popular architecture for DNN acceleration …

A survey on design approaches to circumvent permanent faults in networks-on-chip

S Werner, J Navaridas, M Luján - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
Increasing fault rates in current and future technology nodes coupled with on-chip
components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) …

FSA: An efficient fault-tolerant systolic array-based DNN accelerator architecture

Y Zhao, K Wang, A Louri - 2022 IEEE 40th International …, 2022 - ieeexplore.ieee.org
With the advent of Deep Neural Network (DNN) accelerators, permanent faults are
increasingly becoming a serious challenge for DNN hardware accelerator, as they can …

A survey on energy-efficient methodologies and architectures of network-on-chip

A Abbas, M Ali, A Fayyaz, A Ghosh, A Kalra… - Computers & Electrical …, 2014 - Elsevier
Integration of large number of electronic components on a single chip has resulted in
complete and complex systems on a single chip. The energy efficiency in the System-on …

Fault-tolerant dynamic task mapping and scheduling for network-on-chip-based multicore platform

N Chatterjee, S Paul, S Chattopadhyay - ACM Transactions on …, 2017 - dl.acm.org
In Network-on-Chip (NoC)-based multicore systems, task allocation and scheduling are
known to be important problems, as they affect the performance of applications in terms of …

Review of network on chip routing algorithms

K Ahmad, M Sethi - EAI Endorsed Transactions on Context-aware Systems …, 2020 - eudl.eu
Abstract System on chip (SoC) is an integrated circuit in which components are
communicating through the bus interconnection system. Network on chip (NoC) is a …

Towards graceful aging degradation in NoCs through an adaptive routing algorithm

K Bhardwaj, K Chakraborty, S Roy - Proceedings of the 49th Annual …, 2012 - dl.acm.org
Continuous technology scaling has made aging mechanisms such as Negative Bias
Temperature Instability (NBTI) and electromigration primary concerns in Network-on-Chip …

A multi-objective model oriented mapping approach for NoC-based computing systems

C Wu, C Deng, L Liu, J Han, J Chen… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
In this paper, a multi-objective, ie, reliability, communication energy, performance, co-
optimization model oriented mapping approach is proposed to find optimal mappings when …

A fault-tolerant low-energy multi-application mapping onto NoC-based multiprocessors

F Khalili, HR Zarandi - 2012 IEEE 15th International …, 2012 - ieeexplore.ieee.org
This paper proposes a fault-tolerant multi-application mapping technique in NoC-based
multiprocessor platforms. The proposed mapping technique is composed of two main parts …

Fault-aware routing approach for mesh-based Network-on-Chip architecture

A Gogoi, B Ghoshal, K Manna - Integration, 2023 - Elsevier
Aggressive communication among cores in multi-core architectures leads to excessive
workload on the components which often degrades the normal functionality and induces …