Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess
timing margin but suffer from the short-path (SP) issue where SPs must be padded to exceed …

In-situ timing error detection and correction (EDAC) structure is widely adopted in timing-
error resilient circuits to reduce the conservative timing guardband induced by process …

Buffer insertion to remove hold violations at multiple process corners is addressed for the
first time. The problem is formulated as integer linear programming (ILP); it is combined with …

Resilient design techniques are used to (i) ensure correct operation under dynamic
variations and to (ii) improve design performance (eg, timing speculation). However …

Resilient design techniques are used to (i) ensure correct operation under dynamic
variations; and (ii) improve design performance (eg, through timing speculation). However …

Razor is a milestone in the field of Error Detection&Correction strategies for low-power
operation. Despite the impressive level of maturity, its application on circuits other than …

Abstract This paper introduces Approximate Error Detection-Correction (AED-C), an error
management scheme suited to adaptive power management on error resilient applications …

An ECO hold time? xing method ful? lls a short path padding in a placed and routed design
by a minimum capacitance insertion. In the method, a padding value determination step …

Resilient circuits based on timing error detection and correction can mitigate the timing
margin effectively, but usually at a cost of extra area overhead. One of the major sources of …

An efficient implementation of voltage over-scaling policies for ultra-low power ICs passes
through the design of on-chip Error Detection and Correction (EDC) mechanisms that can …