VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic
algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The …

This handbook provides an up-to-date compendium of fundamental computer science
topics, techniques, and applications. Along with updating and revising many of the existing …

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

The authors describe KOAN and ANAGRAM II, new tools for device-level analog placement
and routing. Analog layout tools that merely apply known digital macrocell techniques fall …

The current status of VLSI layout and directions for future research are addressed, with
emphasis on the authors' own work. Necessary terminology and definitions and, whenever …

From the Publisher: This text treats the physical design of very large scale integrated circuits
gradually and systematically. It examines the design problem and the design process with …

Unlike classical floorplanning that usually handles only block packing to minimize silicon
area, modern very large scale integration (VLSI) floorplanning typically needs to pack blocks …

A methodology for the automatic synthesis of full-custom IC layout with analog constraints is
presented. The methodology guarantees that all performance constraints are met when …

We present a branch-and-bound placement technique for building block layout that
effectively searches for an optimal placement in the whole solution space. We first describe …

Analog circuit design is often the bottleneck when designing mixed analog-digital systems. A
Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits presents a …