WH Wolf - IEEE transactions on computer-aided design of …, 1989 - ieeexplore.ieee.org
Techniques are described for applying the mechanisms of object-oriented programming languages to hardware description. Some object-oriented language mechanisms, like …
P Cappello, K Steiglitz - IEEE transactions on circuits and …, 1985 - ieeexplore.ieee.org
Completely pipelined inner product architectures are presented for FIR filtering and linear transformation. The designs use only full adders, organized to form multipliers. By cascading …
V Vijayan - Proceedings of the second annual symposium on …, 1986 - dl.acm.org
In this paper, we conslder certain geometric problems regarding planar graphs. We are interested in straight line embeddings of planar graphs that satisfy certain angle constraints …
The doctrine of computer life is not congenial to many people. Often they have not thought in any depth about the idea, and it necessarily disturbs their psychological and intellectual …
K Iwano, K Steiglitz - IEEE transactions on acoustics, speech …, 1986 - ieeexplore.ieee.org
We study the problem of optimizing the transistor sizes in the one-bit nMOS full adder either isolated or embedded in a regular array. A local optimization method that we call the critical …
AR Newton - Design Systems for VLSI Circuits, 1987 - books.google.com
Symbolic IC design has been in use since the early 1970s [LAR71]. The use of symbols to represent IC devices began as a logical mapping between the electrical schematic of circuits …
CU Smith, RR Gross - Proceedings of the IEEE, 1986 - ieeexplore.ieee.org
Recent research on the explicit transfer of technology used in computer-aided design (CAD) tools and design methodologies is reported. First, several examples are given of …
PDL++, an optimizing generator language for register transfer systems lets users write C++ programs that generate register transfer machines and optimize the logic design using misII …
K Steiglitz, R Morita - ICASSP'85. IEEE International …, 1985 - ieeexplore.ieee.org
We describe the design and testing of an 18-processor chip that implements the update rule for a fixed one-dimensional binary-valued cellular automaton. The VLSI design was done in …