In this paper, we examine a ready-to-use, robust, and computationally fast fixed-size
memory pool manager with no-loops and no-memory overhead that is highly suited towards …

This paper presents a modified technique of simulated annealing, based on machine
learning for effective multi-objective design space exploration in High Level Synthesis …

This paper presents an efficient technique to perform design space exploration of a
multiprocessor platform that minimizes the number of simulations needed to identify a Pareto …

In the recent Internet-of-Things (IoT) era where biomedical applications require continuous
monitoring of relevant data, edge computing keeps gaining more and more importance …

In this chapter, we present the development of a novel task scheduling algorithm for the
design-time scheduling phase of our two-phase TCM framework. Scheduling has different …

We address the problem of custom Dynamic Memory Management (DMM) in Multi-
Processor System-on-Chip (MPSoC) architectures. Customization is enabled through the …

The present disclosure relates to a memory hierarchy for a system-in-package. An example
memory hierarchy is con nectable to a processor via a memory management unit arranged …

Modern consumer devices must execute multimedia applications that exhibit high resource
utilization. In order to efficiently execute these applications, the dynamic memory subsystem …

Modern embedded systems in mobile and multimedia applications offer a wide range of
features. They can also communicate to different devices using different standards which …

Multiprocessor system-on-chip (MPSoCs) have attracted significant attention since they are
recognized as a scalable paradigm to interconnect and organize a high number of cores …