A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter
This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
A 0.65-V 12–16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM
This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
A Type-I Sub-Sampling PLL With a Footprint and −255-dB FOM
A Sharkia, S Mirabbasi… - IEEE Journal of Solid-State …, 2018 - ieeexplore.ieee.org
A dual-loop LC-voltage-controlled oscillator (VCO) based frequency synthesizer, composed
of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, subsampling …
of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, subsampling …
A novel adaptive bandpass filter based PLL for grid synchronization under distorted grid conditions
K Sridharan, BC Babu - IEEE Transactions on Instrumentation …, 2022 - ieeexplore.ieee.org
In the current scenario, the integration of a renewable energy sources (RESs) with variable
power production into power grids requires a power converter with robust control …
power production into power grids requires a power converter with robust control …
Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature]
Fast settling phase locked loops (PLLs) play a pivotal role in many applications requiring
rapid attainment of a stable frequency and phase. In modern communication standards …
rapid attainment of a stable frequency and phase. In modern communication standards …
[HTML][HTML] Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art
This article overviews the design considerations and state-of-the-art of the ring voltage-
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …
A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction
This paper presents a type-II reference-sampling (RS) phase-locked loop (PLL) exploiting a
novel gain-boosting reference-sampling phase detector (RSPD) to reduce the in-band …
novel gain-boosting reference-sampling phase detector (RSPD) to reduce the in-band …
Spur minimization techniques for ultra-low-power injection-locked transmitters
Frequency multiplying wireless transmitters (TX) employing harmonic injection-locked
technique benefit from high energy efficiency and less hardware complexity but largely …
technique benefit from high energy efficiency and less hardware complexity but largely …
Reference spur reduction techniques for a phase-locked loop
This paper presents the reference spur reduction techniques for an analog phase-locked
loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage …
loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage …
A 0.8-V, 2.55-GHz, 2.62-mW charge-pump PLL with high spectrum purity
L Liu, Y Ji, X Liao, Z Qin, H Liang - IEEE Transactions on Very …, 2022 - ieeexplore.ieee.org
This article presents a low supply voltage and low-power charge-pump phase-locked loop
(CPPLL) with phase noise (PN) improvement and reference spur reduction techniques. The …
(CPPLL) with phase noise (PN) improvement and reference spur reduction techniques. The …