CODEBench: A neural architecture and hardware accelerator co-design framework

S Tuli, CH Li, R Sharma, NK Jha - ACM Transactions on Embedded …, 2023 - dl.acm.org
Recently, automated co-design of machine learning (ML) models and accelerator
architectures has attracted significant attention from both the industry and academia …

Highly optimized hardware morphological neural network through stochastic computing and tropical pruning

JL Rosselló, J Font-Rosselló, CF Frasser… - IEEE Journal on …, 2022 - ieeexplore.ieee.org
This work aimed to enhance a previous neural network hardware implementation based on
an efficient combination of Stochastic Computing (SC) and Morphological Neural Networks …

Hardware implementation of stochastic computing-based morphological neural systems

JL Rosselló, J Font-Rosselló, CF Frasser… - … on Circuits and …, 2022 - ieeexplore.ieee.org
In this work we propose a new methodology for neural network hardware implementation
based on an efficient combination of Stochastic Computing and Morphological Neural …

Neuron Network with a Synapse of CMOS transistor and Anti-Parallel Memristors for Low power Implementations

VK Rai, R Sakthivel - Journal of Circuits, Systems and Computers, 2022 - World Scientific
The bio-mimetic structure of a neuron is taken into account for utilizing the
electrophysiological data. These neuron circuits are entertained for the use in digital …

Enhancing Deep Neural Networks in Diverse Resource-Constrained Hardware Settings

S Tuli - 2024 - search.proquest.com
Over the past decade, artificial intelligence (AI) has gained significant interest in industry and
academia. Deep neural network (DNN) models have exploded in size over the years. Wider …