Impact of high-temperature and interface traps on performance of a junctionless tunnel FET

Performance Analysis and Design Comparison of Junctionless TFET: a Review Study

A Mohanty, MA Ahmad, P Kumar, R Kumar - Silicon, 2024 - Springer
Many research is underway in the semiconductor industry. Conventional MOSFETs are
getting replaced with emerging devices such as junctionless field-effect-transistor (JLTFET) …
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Performances of gate stacked heterojunction SELBOX and SOI tunnel FETs including interface trap charges: A simulation study

N Harsha, S Tiwari, R Chaudhary, R Saha - Materials Science and …, 2024 - Elsevier
In this work, the influence of interface trap charges (ITCs) on electrical parameters of gate
stacked heterojunction silicon on insulator Tunnel FET (GSHJ-SOITFET) and GSHJ-TFET on …
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Design, simulation and analog/RF performance evaluation of a hetero-stacked source dual metal T-shaped gate tunnel-FET in thermally variable environments

M Kumar, G Bhaskar, A Chotalia, C Rani… - Microsystem …, 2024 - Springer
In this work, a new Hetero-Stacked Source Dual Metal T-shaped Gate Silicon-on-Insulator
(SOI) TFET (HS-DMTG-TFET) is proposed, exhibiting significantly improved DC …
被引用次数：1 相关文章 所有 2 个版本

Performance optimization of AlGaAs and Al x Ga 1− x As based SM-TM-DG-JL-TFET for an analog/RF applications

R Tamilarasi, S Karthik - Physica Scripta, 2024 - iopscience.iop.org
This study aims to enhance the efficiency of the Double Gate-Junctionless-Tunnel Field
Effect Transistor (DG-JL-TFET) by optimizing the utilization of AlGaAs and GaAs/Si/AlGaAs …
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Enhancing Performance and Versatility of DG-JL-TFET with A1N Piezoelectric Materials for High-Power Applications

R Tamilarasi, S Karthik - 2024 International Conference on …, 2024 - ieeexplore.ieee.org
The purpose of this study is to investigate the incorporation of aluminium nitride (AIN)
piezoelectric materials into double-gate junctionless tunnel field-effect transistors (DG-JL …
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