A review of the gate-all-around nanosheet FET process opportunities
S Mukesh, J Zhang - Electronics, 2022 - mdpi.com
In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET
are reviewed. These innovations span enablement of multiple threshold voltages and …
are reviewed. These innovations span enablement of multiple threshold voltages and …
A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog/digital IC applications
This article critically reviews the fabrication challenges, emerging materials (wafer, high-k
oxide, gate metal, channel materials), dimensional influences, thermal effects, growth …
oxide, gate metal, channel materials), dimensional influences, thermal effects, growth …
A machine learning approach for optimization of channel geometry and source/drain doping profile of stacked nanosheet transistors
Complex nonlinear dependence of ultra-scaled transistor performance on its channel
geometry and source/drain (S/D) doping profile bring obstacles in the advanced technology …
geometry and source/drain (S/D) doping profile bring obstacles in the advanced technology …
Review of nanosheet metrology opportunities for technology readiness
Over the past several years, stacked nanosheet gate-all-around (GAA) transistors captured
the focus of the semiconductor industry and have been identified as the lead architecture to …
the focus of the semiconductor industry and have been identified as the lead architecture to …
Design of GAA nanosheet ferroelectric area tunneling FET and its significance with DC/RF characteristics including linearity analyses
This work reports an emerging structure of gate-all-around ferroelectric area tunneling field-
effect transistor (FATFET) by considering ferroelectric and an-epitaxial layer enveloped …
effect transistor (FATFET) by considering ferroelectric and an-epitaxial layer enveloped …
Stacked SiGe nanosheets p-FET for Sub-3 nm logic applications
The fabrication of vertically stacked SiGe nanosheet (NS) field-effect transistors (FETs) was
demonstrated in this study. The key process technologies involved in this device fabrication …
demonstrated in this study. The key process technologies involved in this device fabrication …
Engineered Vertically Stacked NSFET Charge-Trapping Synapse for Neuromorphic Applications
MH Raza Ansari, N Navlakha… - ACS Applied Electronic …, 2023 - ACS Publications
In this work, a vertically stacked nanosheet FET (NSFET) is engineered for neuromorphic
applications, which consists of nonidentical sheets in the vertical direction. The proposed …
applications, which consists of nonidentical sheets in the vertical direction. The proposed …
Toward monolithic growth integration of nanowire electronics in 3D architecture: a review
L Liang, R Hu, L Yu - Science China Information Sciences, 2023 - Springer
Abstract Quasi-one-dimensional (1D) semiconducting nanowires (NWs), with excellent
electrostatic control capability, are widely regarded as advantageous channels for the …
electrostatic control capability, are widely regarded as advantageous channels for the …
A comparative study on performance of junctionless Bulk SiGe and Si FinFET
X Shi, H Hu, Y Wang, L Wang, N Zhang, B Wang… - Microelectronics …, 2022 - Elsevier
In this paper, the n-type and p-type SiGe junctionless bulk FinFET (SiGe JL-FinFET) with a
high Ge mole fraction (xF> 0.8) was studied for characteristics of a single device and the …
high Ge mole fraction (xF> 0.8) was studied for characteristics of a single device and the …
Physical insights of Si-core-SiGe-shell gate-all-around nanosheet pFET for 3 nm technology node
H Xu, J Yao, Z Yang, L Cao, Q Zhang… - … on Electron Devices, 2023 - ieeexplore.ieee.org
This article presents a physics-based simulation study of a Si-core-SiGe-shell gate-all-
around (GAA) nanosheet FET (NSFET). The numerical simulations employ various models …
around (GAA) nanosheet FET (NSFET). The numerical simulations employ various models …