Sigma-delta modulators: Tutorial overview, design guide, and state-of-the-art survey
JM de la Rosa - IEEE Transactions on Circuits and Systems I …, 2010 - ieeexplore.ieee.org
This paper presents a tutorial overview of ΣΔ modulators, their operating principles and
architectures, circuit errors and models, design methods, and practical issues. A review of …
architectures, circuit errors and models, design methods, and practical issues. A review of …
Next-generation delta-sigma converters: Trends and perspectives
JM de la Rosa, R Schreier, KP Pun… - IEEE Journal on …, 2015 - ieeexplore.ieee.org
This paper presents an overview of emerging circuits and systems techniques which are at
the forefront of the state of the art in ΔΣ modulators, pushing their performance forward and …
the forefront of the state of the art in ΔΣ modulators, pushing their performance forward and …
A 6.5-μW 10-kHz BW 80.4-dB SNDR Gm-C-Based CT ∆∑ Modulator With a Feedback-Assisted Gm Linearization for Artifact-Tolerant Neural Recording
This article presents a G mC-based continuous-time delta–sigma modulator (CTDSM) for
artifact-tolerant neural recording interfaces. We propose the feedback-assisted G m …
artifact-tolerant neural recording interfaces. We propose the feedback-assisted G m …
A 16-mW 78-dB SNDR 10-MHz BW CT ADC Using Residue-Cancelling VCO-Based Quantizer
This paper presents a continuous-time (CT) ΔΣ modulator using a VCO-based internal
quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue …
quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue …
[图书][B] CMOS sigma-delta converters: Practical design guide
JM De la Rosa, R Del Rio - 2013 - books.google.com
A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a
practical guide to their design in nano-scale CMOS for optimal performance. This book …
practical guide to their design in nano-scale CMOS for optimal performance. This book …
A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integrator
This paper presents a novel noise shaping SAR architecture that is simple, robust and low
power. It is fully passive and only needs minor modification to a conventional SAR ADC …
power. It is fully passive and only needs minor modification to a conventional SAR ADC …
A 4 GHz Continuous-Time ADC With 70 dB DR and 74 dBFS THD in 125 MHz BW
M Bolatkale, LJ Breems, R Rutten… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that
absorbs the pole caused by the input capacitance of its 4-bit quantizer and also …
absorbs the pole caused by the input capacitance of its 4-bit quantizer and also …
Analog filter design using ring oscillator integrators
B Drost, M Talegaonkar… - IEEE Journal of Solid …, 2012 - ieeexplore.ieee.org
Integrators are key building blocks in many analog signal processing circuits and systems.
The DC gain of conventional opamp-RC or Gm-C integrators is severely limited by the gain …
The DC gain of conventional opamp-RC or Gm-C integrators is severely limited by the gain …
A Continuous-Time Sturdy-MASH Modulator in 28 nm CMOS
DY Yoon, S Ho, HS Lee - IEEE Journal of Solid-State Circuits, 2015 - ieeexplore.ieee.org
This paper presents a practical way to achieve both wide signal bandwidth and high
dynamic range in a continuous-time (CT) delta-sigma modulator. Quantization noise is …
dynamic range in a continuous-time (CT) delta-sigma modulator. Quantization noise is …
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- M Structure
This article presents a capacitively coupled voltage-controlled oscillator (VCO)-based
sensor readout featuring a hybrid phase-locked loop (PLL)-ΔΣ modulator structure. It …
sensor readout featuring a hybrid phase-locked loop (PLL)-ΔΣ modulator structure. It …