A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry
Future product applications demand increasing performance with reduced power
consumption, which motivates the pursuit of high-performance at reduced operating …
consumption, which motivates the pursuit of high-performance at reduced operating …
Leakage characterization of 10T SRAM cell
This paper presents a technique for designing a low-power and variability-aware SRAM cell.
The cell achieves low power dissipation due to its series-connected tail transistor and read …
The cell achieves low power dissipation due to its series-connected tail transistor and read …
[图书][B] Robust SRAM designs and analysis
This book provides a guide to Static Random Access Memory (SRAM) bitcell design and
analysis to meet the nano-regime challenges for CMOS devices and emerging devices …
analysis to meet the nano-regime challenges for CMOS devices and emerging devices …
Large-scale SRAM variability characterization in 45 nm CMOS
Z Guo, A Carlson, LT Pang, KT Duong… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
Increased process variability presents a major challenge for future SRAM scaling. Fast and
accurate validation of SRAM read stability and writeability margins is crucial for estimating …
accurate validation of SRAM read stability and writeability margins is crucial for estimating …
Low-power near-threshold 10T SRAM bit cells with enhanced data-independent read port leakage for array augmentation in 32-nm CMOS
The conventional six-transistor static random access memory (SRAM) cell allows high
density and fast differential sensing but suffers from half-select and read-disturb issues …
density and fast differential sensing but suffers from half-select and read-disturb issues …
A 130 mV SRAM with expanded write and read margins for subthreshold applications
MF Chang, SW Chang, PW Chou… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
SRAM suffers read-disturb and write failures at a low supply voltage, especially at deep
subthreshold operation. This study proposes a 9T-SRAM cell with a data-aware-feedback …
subthreshold operation. This study proposes a 9T-SRAM cell with a data-aware-feedback …
Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources
We present experimental results of soft errors produced by proton and neutron irradiation of
minimum-size six-transistors (6T) and eight-transistors (8T) bit-cells SRAM memories …
minimum-size six-transistors (6T) and eight-transistors (8T) bit-cells SRAM memories …
Low leakage fully half-select-free robust SRAM cells with BTI reliability analysis
This paper presents two different topologies of 11T SRAM cells with fully half-select-free
robust operation for bit-interleaving implementation. The proposed 11T-1 and 11T-2 cells …
robust operation for bit-interleaving implementation. The proposed 11T-1 and 11T-2 cells …
A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell
This paper presents a technique for designing a variability aware SRAM cell. The
architecture of the proposed cell is similar to the standard 6T SRAM cell with the exception …
architecture of the proposed cell is similar to the standard 6T SRAM cell with the exception …
A 64 Mb SRAM in 32 nm high-k metal-gate SOI technology with 0.7 V operation enabled by stability, write-ability and read-ability enhancements
H Pilo, I Arsovski, K Batson, G Braceras… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology.
The SRAM features a 0.154 μm^2 bit-cell, the smallest to date for a 32 nm SOI product. A 0.7 …
The SRAM features a 0.154 μm^2 bit-cell, the smallest to date for a 32 nm SOI product. A 0.7 …