Asynchronous design has a very promising potential even though it has largely received a
cold reception from industry. Part of this reluctance has been due to the necessity of custom …

A dual clock register based elastic First-In First-Out Architecture is presented for Globally
Asynchronous Locally Synchronous (GALS) Network on Chip interface. The FIFO is …

The open core protocol (OCP) is an openly licensed configurable and scalable interface
protocol for on-chip subsystem communications. The protocol defines read and write …

Integrated circuits often consist of multiple processing elements that are regularly tiled
across the two-dimensional surface of a die. This work presents the design and integration …

This paper presents an FPGA architecture capable of implementing relative timing based
asynchronous designs. Modifications are made to a traditional synchronous FPGA …

G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, eg which
still read as programmed but with threshold less than the program verify threshold or read as …

Power has replaced performance as the primary constraint in modern digital circuits. The
advances in process technology have allowed billions of transistors to be put on a single …

ACHIEVING BACKEND ROBUSTNESS FOR TIMED ASYNCHRONOUS CIRCUITS Page 1
ACHIEVING BACKEND ROBUSTNESS FOR TIMED ASYNCHRONOUS CIRCUITS by William …