A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators
D Filippas, C Peltekis, V Titopoulos… - IEEE …, 2024 - ieeexplore.ieee.org
Convolution neural networks (CNNs) are widely applied in many machine learning
applications. Hardware acceleration for CNNs is crucial, given their high computational …
applications. Hardware acceleration for CNNs is crucial, given their high computational …
Error Checking for Sparse Systolic Tensor Arrays
Structured sparsity is an efficient way to prune the complexity of modern Machine Learning
(ML) applications and to simplify the handling of sparse data in hardware. In such cases, the …
(ML) applications and to simplify the handling of sparse data in hardware. In such cases, the …
ZOR: Zero Overhead Reliability Strategies for AI Accelerators
This research investigates the crucial integration of Neural Network (NN) models with the
architecture of the hardware (HW) accelerator. Unlike existing approaches overlooking this …
architecture of the hardware (HW) accelerator. Unlike existing approaches overlooking this …
Studio e Sviluppo di un algoritmo di routing per FPGA radiation-hardened ottimizzato per GPGPU= Study and Development of a Routing Algorithm for Radiation …
A Saracino - 2024 - webthesis.biblio.polito.it
I Field Programmable Gate Arrays (FPGAs) sono circuiti integrati riprogrammabili un numero
indefinito di volte dopo la produzione. Questa caratteristica permette di adattare il …
indefinito di volte dopo la produzione. Questa caratteristica permette di adattare il …