Programming memristor arrays with arbitrarily high precision for analog computing

W Song, M Rao, Y Li, C Li, Y Zhuo, F Cai, M Wu, W Yin… - Science, 2024 - science.org
In-memory computing represents an effective method for modeling complex physical
systems that are typically challenging for conventional computing architectures but has been …

TEFLON: Thermally Efficient Dataflow-Aware 3D NoC for Accelerating CNN Inferencing on Manycore PIM Architectures

G Narang, C Ogbogu, JR Doppa… - ACM Transactions on …, 2024 - dl.acm.org
Resistive random-access memory (ReRAM)-based processing-in-memory (PIM)
architectures are used extensively to accelerate inferencing/training with convolutional …

SAL: Optimizing the Dataflow of Spin-based Architectures for Lightweight Neural Networks

Y Zhao, S Ma, H Liu, D Li - ACM Transactions on Architecture and Code …, 2024 - dl.acm.org
As the Convolutional Neural Network (CNN) goes deeper and more complex, the network
becomes memory-intensive and computation-intensive. To address this issue, the …

Static Scheduling of Weight Programming for DNN Acceleration with Resource Constrained PIM

X Gao, H Wang, Y Chen, Y Zhang, Z Shen… - ACM Transactions on …, 2024 - dl.acm.org
Most existing architectural studies on ReRAM-based processing-in-memory (PIM) DNN
accelerators assume that all weights of the DNN can be mapped to the crossbar at once …

Energy-Efficient DNN Inferencing on ReRAM-Based PIM Accelerators Using Heterogeneous Operation Units

G Narang, JR Doppa, PP Pande - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Operation Unit (OU)-based configurations enable the design of energy-efficient and reliable
ReRAM crossbar-based Processing-In-Memory (PIM) architectures for Deep Neural Network …

ChainPIM: A ReRAM-Based Processing-in-Memory Accelerator for HGNNs via Chain Structure

W Xiao, J Wang, D Chen, C Shi, X Ling… - … on Computer-Aided …, 2025 - ieeexplore.ieee.org
Heterogeneous graph neural networks (HGNNs) have recently demonstrated significant
advantages of capturing powerful structural and semantic information in heterogeneous …

Trade-off Performance and Energy Efficiency by Optimizing the Data Flow for PIM Architectures

Y Zhao, S Ma, Y Tang, H Liu, D Li - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
The Processing-In-Memory (PIM) architecture becomes a promising candidate for deep
learning accelerators by integrating computation and memory. Most PIM-based studies …

ReShare: A Resource-Efficient Weight Pattern Sharing Scheme for Memristive DNN Accelerators

S Hong, YC Chung - 2024 IEEE International Symposium on …, 2024 - ieeexplore.ieee.org
Memristor crossbar-based computing-in-memory (CIM) has garnered significant attention for
accelerating deep neural networks (DNNs). Although practical operation unit (OU)-based …

Design of The Ultra-Low-Power Driven VMM Configurations for μW Scale IoT Devices

K Takano, T Yajima, S Kawakami - 2023 IEEE 16th …, 2023 - ieeexplore.ieee.org
Operating IoT devices by supplying power from an energy harvester and installing AI
accelerators in IoT devices are required. Nevertheless, conventionally selected architectures …