A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk
Time-interleaved (TI) analog-to-digital converters (ADCs) are an established architecture,
but fundamental problems still exist that prevent replicating the performance of each sub …
but fundamental problems still exist that prevent replicating the performance of each sub …
A comprehensive review of time skew background calibration and mitigation techniques in high‐speed time‐interleaved analog‐to‐digital converters
A significant challenge in designing high‐speed time‐interleaved ADCs (TI‐ADCs) is the
presence of time skew mismatch, resulting from uneven sampling across different channels …
presence of time skew mismatch, resulting from uneven sampling across different channels …
A Generated 4 GS/s 124.6 mW 8× Time-Interleaved SAR-VCO ADC with 9.1 ENOB
Z Liu, B Nikolić - 2024 IEEE European Solid-State Electronics …, 2024 - ieeexplore.ieee.org
This work presents an eight-way time-interleaved SAR-VCO ADC implemented in the Intel
16 process that operates at 4GS/s with 9.1 ENOB resolution. The sub-ADC design combines …
16 process that operates at 4GS/s with 9.1 ENOB resolution. The sub-ADC design combines …