Area and Power Modeling for FPGA-Based Barrel Shifter Using Regression Algorithm

H Prasad, A Kumar - National Academy Science Letters, 2024 - Springer
Data shifting, addressed in this article is an essential operation of arithmetic processors and
array processors used for graphics and video processing applications. This research article …

Design of reversible floating point adder for DSP applications

AN Nagamani, CK Kavyashree, RM Saraswathy… - Proceedings of the …, 2016 - Springer
Motivation for the study of technologies implementing reversible computing methods are that
they offer a potential way to improve the energy efficiency of computers beyond the …

[PDF][PDF] Design of an optimized reversible ternary and binary bidirectional and normalization barrel shifters for floating point arithmetic

NH Nia - Life Sci J, 2012 - fardapaper.ir
One of the most challenging issues in circuit design is power consumption. Designing circuit
using reversible logic is one of the solutions to decrease power loss. Theoretically, a …

Design of an optimized reversible bidirectional barrel shifter

S Nowrin, L Jamal, HMH Babu - 2016 IEEE International …, 2016 - ieeexplore.ieee.org
In this paper, we propose an optimized design of an n-bit reversible bidirectional barrel
shifter, where n is an integer power of two. The proposed bidirectional barrel shifter can shift …

Novel nanometric reversible low power bidirectional universal logarithmic barrel shifter with overflow and zero flags

N Hosseininia, S Boroumand… - Journal of Circuits …, 2015 - World Scientific
One of the most important issues in designing VLSI circuits is power consumption.
Reversible logic which is widely utilized in quantum computing, low power CMOS design …

Optimized fault tolerant designs of the reversible barrel shifters using low power MOS transistors

M Shamsujjoha, F Hossain, MNY Ali… - Journal of Computational …, 2015 - Springer
This paper demonstrates the reversible logic synthesis for the unidirectional, bidirectional
and universal barrel shifters. The proposed shifters are constructed using only Fredkin and …

Design and implementation of low power mitchell algorithm based logarithmic multiplier

HV Ranjitha, KS Pooja… - 2017 2nd IEEE …, 2017 - ieeexplore.ieee.org
Multiplication is a significant operation in signal processing but slow and complex leading to
high power consumption and area. Digital Signal Processing repetitively uses multiplication …

A 4-bit Barrel Shifter Design using Diverse Logic Style

P Tiwari, A Kumar - … on Advances in Computing and Future …, 2021 - ieeexplore.ieee.org
Very–low-power CMOS IC design is needed for any communication systems. The system's
performance is measured in terms of less power dissipation, small delay and small area. In …

[PDF][PDF] Design and Optimization of Reversible Carry Look Ahead Adder Circuit

AA Bharadwaj, HR Madan, IK Soares… - International Journal of … - academia.edu
Power dissipation is a prominent factor in limiting the chip area. Conventional computing
has been facing many challenges from the last couple of decades. The device scaling …

Post synthesis optimization of reversible logic functions with extended template matching

HV Jayashree, VK Agrawal… - … Conference on Circuits …, 2014 - ieeexplore.ieee.org
Research affinity towards Reversible Computing is increasing day to day due to its lower
energy dissipation computing capability. To evaluate any reversible function it is necessary …