An accurate prediction of remaining useful lifetime (RUL) in high reliability and safety
electronic systems is required due to its wide use in industrial applications. In this paper, we …

Regular and redundant through-silicon via (TSV) interconnects are used in fault tolerance
techniques of 3-D IC. However, the fabrication process of TSVs results in defects that reduce …

This paper presents an in-depth analysis of resistive open and resistive bridge defects
behavior under process, voltage and temperature (PVT) variation using delay test. Using …

Power switches are used as a part of the power-gating technique to reduce the leakage
power of a design. To the best of our knowledge, this is the first report in open literature to …

This paper shows that existing delay-based testing techniques for power gating exhibit fault
coverage loss due to unconsidered delays introduced by the structure of the virtual voltage …

为真实模拟集成电路中的桥接故障并评价测试集质量, 提出一种基于静态电源电流(IDDQ)
测试的逻辑电路门内电阻式桥接故障仿真算法. 首先, 针对该故障类型, 提出一种覆盖率评价标准 …

As part of the gating technique, the power switches are used to decrease/reduce the
leakage power of a design. Accurate diagnosis of the power switches remains a subject of …

This paper shows that existing delay-based testing techniques for power gating exhibit both
fault coverage and yield loss due to deviations at the charging delay introduced by the …

SPICE offers an accurate method of simulating defect behavior. However, as demonstrated
by recent research, it requires long computation time to simulate defect behavior, when …

A defect-based bridge fault represents the faulty behavior of an interconnect short defect
obtained by SPICE simulating the two shorted cells with the short defect injected. In this …