Capacitive and inductive tsv-to-tsv resilient approaches for 3d ics

PM Yaghini, A Eghbal, SS Yazdi… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
TSV-to-TSV coupling is known to be a significant detriment to signal integrity in three-
dimensional (3D) IC architectures. Designing a reliable Through-Silicon Via is critical in …

Deadlock verification of cache coherence protocols and communication fabrics

F Verbeek, PM Yaghini, A Eghbal… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Cache coherence plays a major role in manycore systems. The verification of deadlocks is a
challenge in particular, because deadlock freedom is an emerging property. Formal …

[PDF][PDF] A survey for silicon on chip communication

KA Kumar, P Dananjayan - Indian Journal of Science and …, 2017 - academia.edu
Abstract Objectives: Network on Chip (NoC) has been emerging area as communication is
very complex at Chip Multi Processor and it has become more popular due to its high …

Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services

MAJ Sethi, FA Hussin, NH Hamid - Integration, 2016 - Elsevier
Abstract Best Effort (BE) and Guaranteed Throughput services (GT) are the two broad
categories of communication services provided in NoC. Few of the existing NoC …

[图书][B] Bio-inspired Fault-tolerant Algorithms for Network-on-chip

MAJ Sethi - 2020 - taylorfrancis.com
Network on Chip (NoC) addresses the communication requirement of different nodes on
System on Chip. The bio-inspired algorithms improve the bandwidth utilization, maximize …

[图书][B] Reliability enhancement of many-core processors

M SeyyedHosseini - 2017 - search.proquest.com
Many-core systems are of great importance for building the exascale computing machine
targeted for 2020. Last-Level Cache (LLC), as the largest on-chip shared memory in many …

Three-Dimensional NoC Reliability Evaluation Automated Tool (TREAT)

A Eghbal - 2016 - escholarship.org
Technology scaling and higher operational frequencies are no longer sustainable at the
same pace as before. The processor industry is rapidly moving from a single core with high …

[图书][B] Resilient 3D network-on-chip design and analysis

PM Yaghini - 2016 - search.proquest.com
Like every other major changes in computer architecture, exascale computing, targeted for
2020, requires dramatic and unanticipated shifts in different perspectives. The biggest …

[PDF][PDF] Analysis and Design of Novel Secured NoC for High Speed Communications

S Rekha, AM Bhavikatti - Indian Journal …, 2017 - sciresol.s3.us-east-2.amazonaws …
Abstract Background/Objectives: Mainstream electronic designs are realized by System on
Chip (SOC) that pushes the limits of integration. Network–On-Chip (NOC) for high speed is …

[PDF][PDF] CAFT: Cost-aware and Fault-tolerant routing algorithm in 2D mesh Network-on-Chip

A Reza, P Jolani, M Reshadi - Journal of Advances in Computer …, 2019 - academia.edu
By increasing, the complexity of chips and integrafing more components into a chip has
made network–on-chip known as an important infrastructure for network communicafions on …