Power consumption of digital systems may increase significantly during testing. In this paper,
systems equipped with a scan-based built-in self-test like the STUMPS architecture are …

Test data compression and test resource partitioning (TRP) are necessary to reduce the
volume of test data for system-on-a-chip designs. We present a new class of variable-to …

This paper presents an overview of an intelligence platform we have built to address threat
hunting and incident investigation use-cases in the cyber security domain. Specifically, we …

The unprecedented urbanization and the staggering development of modern information
and communication technologies (ICT) demonstrate that the concept of Smart City is …

This paper presents a new compression method for embedded core-based system-on-a-
chip test. In addition to the new compression method, this paper analyzes the three test data …

CASP, Concurrent Autonomous chip self-test using S tored test P atterns, is a special kind of
self-test where a system tests itself concurrently during normal operation without any …

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In this paper a new scheme for deterministic and mixed mode scan-based BIST is
presented. It relies on a new type of test pattern generator which resembles a programmable …

This paper presents a new test-data compression technique that uses exactly nine
codewords. Our technique aims at precomputed data of intellectual property cores in system …

This paper presents an innovative method for inserting test points in the circuit-under-test to
obtain complete fault coverage for a specified set of test patterns. Rather than using …